DRAM Timing & Command Protocols

Section goal

JEDEC command timing, activate/precharge/read/write sequencing, timing parameters, turnaround penalties, and scheduler-visible constraints.

This section trains how to reason from traffic behavior to DRAM mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. jedec-command-sequencing/ - JEDEC Command Sequencing

2. trcd-trp-tras-trc-timing/ - tRCD / tRP / tRAS / tRC Timing

3. read-write-turnaround/ - Read/Write Turnaround

4. timing-closure-and-guardbands/ - Timing Closure and Guardbands

Related topics

• DRAM & Memory Design course hub

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

• timing-parameter budget table

• command-bus utilization timeline

• tFAW window violation log

• read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

• Audit command spacing against JEDEC minimums and guards

• Track bus-direction switches and hidden dead cycles

• Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?