DRAM & Memory Design · All levels

JEDEC Command Sequencing

DRAM Timing & Command Protocols: Track each bank's open-row state and gate scheduler decisions so ACT obeys tRRD/tFAW windows, READ/WRITE obey post-ACT latency (tRCD), and PRE is delayed until row-active minimums are met.

What this topic teaches

JEDEC Command Sequencing turns DRAM theory into production-grade review decisions. Track each bank's open-row state and gate scheduler decisions so ACT obeys tRRD/tFAW windows, READ/WRITE obey post-ACT latency (tRCD), and PRE is delayed until row-active minimums are met.

The main objective is to identify where the first loss starts in the memory service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior DRAM work is less about isolated register tuning and more about cross-layer causality: traffic shape, command stream legality, bank behavior, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions. regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

diagram

DRAM CELL DIAGRAM - JEDEC Command Sequencing

                bitline (BL)
                    |
           +--------+--------+
wordline --| access transistor|-- storage capacitor (Ccell)
           +--------+--------+
                    |
                  ground

Read:   BL precharge -> WL on -> tiny delta-V -> sense amp amplifies
Write:  drive BL -> WL on -> charge/discharge Ccell -> WL off

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions.

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

ACT->READ->PRE waveform (Jedec Command Sequencing)

diagram

CORE JEDEC ROW TIMING WAVEFORM

time ---> ------------------------------------------------------------>
CMD      ACT ------------------- READ ------- READ -------- PRE -------
WL       ____/^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\__________
BL       === precharge === tiny-dV === sense/restore === equalize ====
STATE    IDLE   ROW_OPEN(wait tRCD)  COL_ACCESS    ROW_OPEN   PRECHG

Constraints:
ACT->READ >= tRCD
ACT->PRE  >= tRAS
PRE->ACT  >= tRP
same-bank ACT->ACT >= tRC

ACT spacing windows (tRRD/tFAW) (Jedec Command Sequencing)

diagram

ACT THROTTLE WINDOW (power/current guardrail)

time ---> ----------------------------------------------------->
ACT cmds   A0      A1      A2      A3      A4
           |-------|-------|-------|-------|
             >=tRRD between adjacent ACTs

Rolling window tFAW:
[--------------------  tFAW  --------------------]
Within any such window, ACT count <= 4 (device dependent policy).

If A4 lands before A0 exits tFAW window, scheduler must stall.

Read/write turnaround bubbles (Jedec Command Sequencing)

diagram

DQ DIRECTION TURNAROUND

time ---> -------------------------------------------------------------->
CMD      READ ---- READ ---- (bubble) ---- WRITE --- WRITE -- (bubble) --
DQ dir    R        R           Z            W        W          Z
DQS       r strobe active      idle         w strobe active     idle

R->W and W->R switches consume mandatory gap cycles
(tWTR, write recovery, and controller/PHY pipeline offsets).

Array hierarchy context

diagram

ARRAY HIERARCHY MAP - JEDEC Command Sequencing

[Channel]
   |
[DIMM/Package]
   |
[Rank]
   |
[Bank Group]
   |
[Bank]
   |
[Subarray]
   |
[Row + Column Decode]
   |
[Cell Mat + Sense Amps]

Lens: map locality decisions to activate/precharge cost.

Command timing context

diagram

COMMAND TIMING DIAGRAM - JEDEC Command Sequencing

time --->    t0      t1      t2      t3      t4      t5
cmd bus   |  ACT  |   RD  |   WR  |  PRE  |  REF  |  ACT
row state | open  | open  | open  | close | all   | open

key checks:
- ACT->RD >= tRCD
- RD data return >= CL
- WR->PRE >= tWR
- PRE->ACT >= tRP

Controller queue context

diagram

CONTROLLER QUEUE VIEW - JEDEC Command Sequencing

read queue : [R12 bank0 row88] [R13 bank2 row88] [R14 bank0 row12]
write queue: [W44 bank3 row90] [W45 bank3 row90]

scheduler tick:
1) prioritize ready row hits
2) cap write-drain burst
3) age outstanding reads

issue stream:
cycle 40 -> RD bank0 row88 (hit)
cycle 41 -> RD bank2 row88 (parallel bank group)
cycle 42 -> ACT bank0 row12 (miss prepare)

Ownership layers

diagram

MEMORY OWNERSHIP LAYERS - JEDEC Command Sequencing

artifact area     owner
----------------  ----------------------------
architecture    Memory controller microarchitecture
controller FW   Command scheduler design
verification    DRAM subsystem verification
silicon bringup TBD

Rule: every signoff metric has a named accountable owner.

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

Primary metric: Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions..
Primary artifact: Per-cycle command legality matrix and bank-state timeline showing ACT -> READ/WRITE -> PRE transitions under JEDEC timing windows..
Owners to include: Memory controller microarchitecture, Command scheduler design, DRAM subsystem verification.
One reproducible failing traffic slice plus one stable comparator capture.
One command legality timeline that isolates first failing transition.
One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

diagram

BANDWIDTH vs LATENCY CURVE - JEDEC Command Sequencing

latency
  ^
  |  low-load region
  |      *
  |        *
  |          *
  |            *         knee
  |              *      *
  |                *   *
  |                  ***
  +----------------------------------------------> bandwidth demand
     stable QoS          queue growth / saturation

Use the knee to set safe operating headroom.

Root-cause decision tree

diagram

ROOT CAUSE TREE - JEDEC Command Sequencing

Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Key takeaways

Prove first failing transition before touching broad tuning policies.
Tie command-level behavior to application-visible QoS outcomes.
Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

Optimizing average GB/s while p99 latency and fairness degrade.
Comparing traces without fixed firmware, timing profile, and thermal tags.
Declaring closure without reliability and retrain robustness checks.

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

diagram

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

timing-parameter budget table
command-bus utilization timeline
tFAW window violation log
read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

Audit command spacing against JEDEC minimums and guards
Track bus-direction switches and hidden dead cycles
Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.

Practice this lesson