JEDEC Command Sequencing: Review Checklist

Review checklist

Review Checklist for JEDEC Command Sequencing focuses on Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

• Workload scope and SLA targets are explicit.

• Environment tags are locked and reproducible.

• First failing transition is proven by command-level evidence.

• Owner and rollback criteria are documented.

• Validation matrix covers performance, stability, and reliability.

• Owners signed: Memory controller microarchitecture, Command scheduler design, DRAM subsystem verification.

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

• timing-parameter budget table

• command-bus utilization timeline

• tFAW window violation log

• read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

• Audit command spacing against JEDEC minimums and guards

• Track bus-direction switches and hidden dead cycles

• Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Review checklist explanation

A checklist here protects against false closure. Every item should map to a known memory failure mode.

For JEDEC Command Sequencing, minimum checklist: workload scope, Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions., artifact evidence (Per-cycle command legality matrix and bank-state timeline showing ACT -> READ/WRITE -> PRE transitions under JEDEC timing windows.), bottleneck class, owner, rollback path, and corner-matrix validation.

If controller or firmware changed, include fairness and RAS checks. If PHY or package assumptions changed, include SI/PI and thermal guardband evidence.