JEDEC Command Sequencing: Comparison Matrix

Comparison matrix

Tighter timing improves throughput but increases sensitivity to SI, PVT drift, and training spread.

Use the matrix as a reasoning aid, not as a simplistic scorecard. DRAM choices are workload-sensitive: the same policy can be right for bandwidth-oriented streaming, wrong for latency-critical bursts, and risky for long-haul reliability.

+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Conservative     | high robustness | lower peak     | new platform   |
| Balanced         | good efficiency | needs telemetry | mixed workloads |
| Aggressive       | max throughput | tail sensitivity | bounded SKUs   |
| Hardening        | field resilience | overhead cost  | safety-critical |
+------------------+----------------+----------------+----------------+

When to choose each approach

• Choose policy from measured conflict profile, SLA targets, and reliability budget

Interview traps

• Copying scheduler recipes across unrelated traffic mixes

• Ignoring coupling between turnaround control, refresh policy, and fairness

Comparison reference

DRAM EVIDENCE MATRIX - JEDEC Command Sequencing

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| row-hit/miss + ACT/PRE mix    | locality and row-state cost    | lane-level capture integrity   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| JEDEC legality + bus timeline | timing-window pressure         | root cause by itself           | correlate with traffic map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot addresses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

• timing-parameter budget table

• command-bus utilization timeline

• tFAW window violation log

• read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

• Audit command spacing against JEDEC minimums and guards

• Track bus-direction switches and hidden dead cycles

• Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

JEDEC Command Sequencing should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

Track each bank's open-row state and gate scheduler decisions so ACT obeys tRRD/tFAW windows, READ/WRITE obey post-ACT latency (tRCD), and PRE is delayed until row-active minimums are met. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as Per-cycle command legality matrix and bank-state timeline showing ACT -> READ/WRITE -> PRE transitions under JEDEC timing windows..

JEDEC timing is the exposed face of underlying analog settle and power-window constraints. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.