JEDEC Command Sequencing: Worked Example

Worked example

Worked Example for JEDEC Command Sequencing focuses on Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

A field regression flags Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions.. Proper triage locks environment tags, compares baseline vs failing traces, isolates first repeated loss transition, and validates one bounded mitigation before release.

This pattern prevents reactive tuning. The goal is to preserve both performance and reliability while avoiding hidden regressions that appear only at corner conditions.

System view

CONTROLLER QUEUE VIEW - JEDEC Command Sequencing

read queue : [R12 bank0 row88] [R13 bank2 row88] [R14 bank0 row12]
write queue: [W44 bank3 row90] [W45 bank3 row90]

scheduler tick:
1) prioritize ready row hits
2) cap write-drain burst
3) age outstanding reads

issue stream:
cycle 40 -> RD bank0 row88 (hit)
cycle 41 -> RD bank2 row88 (parallel bank group)
cycle 42 -> ACT bank0 row12 (miss prepare)

ACT->READ->PRE waveform (Jedec Command Sequencing)

CORE JEDEC ROW TIMING WAVEFORM

time ---> ------------------------------------------------------------>
CMD      ACT ------------------- READ ------- READ -------- PRE -------
WL       ____/^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\__________
BL       === precharge === tiny-dV === sense/restore === equalize ====
STATE    IDLE   ROW_OPEN(wait tRCD)  COL_ACCESS    ROW_OPEN   PRECHG

Constraints:
ACT->READ >= tRCD
ACT->PRE  >= tRAS
PRE->ACT  >= tRP
same-bank ACT->ACT >= tRC

1. Capture baseline and failing command traces under fixed metadata.

2. Verify row-hit/miss mix, turnaround cadence, and refresh impact.

3. Collect Per-cycle command legality matrix and bank-state timeline showing ACT -> READ/WRITE -> PRE transitions under JEDEC timing windows..

4. Patch one bounded fix with explicit owner signoff.

5. Re-run closure matrix and choose ship/rollback.

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

• timing-parameter budget table

• command-bus utilization timeline

• tFAW window violation log

• read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

• Audit command spacing against JEDEC minimums and guards

• Track bus-direction switches and hidden dead cycles

• Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Worked-example reasoning

Suppose Issue legal ACT/PRE/READ/WRITE command streams while respecting bank-group cadence (tRRD, tFAW, tCCD) and per-bank state transitions. regresses on a production workload. A shallow response only tweaks timing or queue weights. A deeper response compares baseline and failing traces, then identifies the first repeated loss mechanism in Track each bank's open-row state and gate scheduler decisions so ACT obeys tRRD/tFAW windows, READ/WRITE obey post-ACT latency (tRCD), and PRE is delayed until row-active minimums are met..

If command waste dominates, inspect row policy and turnaround cadence. If blocked cycles dominate, inspect refresh scheduling and QoS windows. If margin loss dominates, inspect lane shmoo and thermal drift.

Only then choose a bounded fix: mapping update, scheduler policy change, refresh strategy adjustment, firmware retrain rule, PHY calibration, or package/SI correction.