DRAM & Memory Design · All levels
DRAM Timing & Command Protocols: Tricky Q&A
Senior interview and review questions for DRAM Timing & Command Protocols.
Section Q&A bank
Use these drills after completing all topics in DRAM Timing & Command Protocols. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why does a controller track both tRRD and tFAW instead of only one activate limit?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: Why does a controller track both tRRD and tFAW instead of only one activate limit?
A:
tRRD constrains spacing between consecutive ACT commands, while tFAW limits how many ACTs fit in a rolling window; both are required to prevent over-aggressive row activation bursts.
FOLLOW-UP TRAP: Treating tFAW as optional if tRRD already passes.What does tRCD practically protect in the ACT -> READ/WRITE sequence?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: What does tRCD practically protect in the ACT -> READ/WRITE sequence?
A:
It guarantees enough delay after ACT before column commands so sense-amplifier and row activation are stable for data access.
FOLLOW-UP TRAP: Issuing READ/WRITE immediately after ACT because row is 'logically open.'How are tRAS, tRP, and tRC related during same-bank reuse?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: How are tRAS, tRP, and tRC related during same-bank reuse?
A:
A row must stay active at least tRAS, then PRE must complete for tRP, and the next ACT to that bank cannot violate the full row-cycle interval tRC.
FOLLOW-UP TRAP: Optimizing PRE timing while forgetting same-bank ACT spacing.Why can read/write turnaround dominate bandwidth loss even when row-hit rate is high?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: Why can read/write turnaround dominate bandwidth loss even when row-hit rate is high?
A:
Direction changes on the DQ bus introduce mandatory dead cycles and recovery delays, so frequent R<->W switching creates bubbles despite good row locality.
FOLLOW-UP TRAP: Assuming row-hit optimization alone removes throughput penalties.What should be included in a robust DRAM timing guardband strategy?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: What should be included in a robust DRAM timing guardband strategy?
A:
Programmable margin on key timings (tRCD, tRP, tRAS, tRC, tRRD, tFAW and turnaround knobs) tied to PVT, SI uncertainty, and PHY training spread.
FOLLOW-UP TRAP: Applying one fixed margin without speed-bin or condition sensitivity.Which artifact best proves scheduler-visible timing correctness?
diagram
[INT][DRAM][TIMING-PROTOCOLS]
Q: Which artifact best proves scheduler-visible timing correctness?
A:
A command-level legality checker with assertion coverage showing no timing-window violations under stress traffic and mixed bank-group scenarios.
FOLLOW-UP TRAP: Relying only on average bandwidth metrics.Q&A drill guide
diagram
WORKLOAD -> DRAM SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
COMMAND TIMING SEQUENCE
ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACTKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.