tRCD / tRP / tRAS / tRC Timing: Debug Playbook

Debug playbook

Debug Playbook for tRCD / tRP / tRAS / tRC Timing focuses on Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

DRAM debug should narrow from broad symptom to one dominant mechanism. Avoid mixed-knob sweeps that produce accidental wins without causal confidence.

1. Freeze workload seed, firmware image, timing profile, and thermal setup.

2. Find first failing transition in command timeline.

3. Classify mechanism: locality loss, legality pressure, queue policy, margin drift, or RAS behavior.

4. Build focused reproducer for top hypothesis.

5. Apply minimal reversible fix and define rollback gate.

6. Re-run full performance + reliability matrix.

Debug decision tree

ROOT CAUSE TREE - tRCD / tRP / tRAS / tRC Timing

Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing. regressed
        |
reproducible with fixed seed?
      /               \
    no                 yes
    |                   |
testbench noise    localize bottleneck
                    /              \
               command path       data path
                 |                  |
             scheduler/FSM      PHY/timing/noise
                 |                  |
             timing limits      training/calibration

Stop at first failing mechanism, then patch and re-measure.

Review memo template

DRAM REVIEW MEMO - DRAM Timing & Command Protocols / tRCD / tRP / tRAS / tRC Timing

1. Symptom
   - Watched metric: Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing.
   - Failing traffic slice: <workload/phase/class>
   - First failing transition: <row-hit/row-conflict/turnaround/refresh/training>
   - Revision tags: <firmware/controller/timing/board/package>

2. Mechanism hypothesis
   - Primary mechanism: Model row lifecycle constraints explicitly: ACT-to-CAS >= tRCD, ACT-to-PRE >= tRAS, PRE-to-next-ACT >= tRP, and ACT-to-next-ACT(same bank) >= tRC while coordinating neighboring-bank limits via tRRD/tFAW.
   - Competing hypotheses: <mapping, scheduling, PHY margin, SI/PI, reliability policy>
   - Missing evidence: <command trace, queue snapshot, lane margins, CE/UE logs>

3. Proposed action
   - Smallest reversible change: <policy/register/firmware/flow>
   - Expected movement: <p99 latency, effective bandwidth, stability>
   - Regression risk: fairness, thermal drift, training robustness, field reliability

4. Signoff
   - Re-run artifact: Timing budget worksheet and assertion set for tRCD, tRP, tRAS, tRC, tRRD, and tFAW checks across random and stress traffic.
   - Required owners: Memory controller timing architecture, DRAM timing-model validation, Performance and correctness verification
   - Final decision: ship, bounded rollout, rollback, or escalate

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

• timing-parameter budget table

• command-bus utilization timeline

• tFAW window violation log

• read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

• Audit command spacing against JEDEC minimums and guards

• Track bus-direction switches and hidden dead cycles

• Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Principal DRAM review addendum

tRCD / tRP / tRAS / tRC Timing should be read as an end-to-end memory behavior, not as a single block definition. A production DRAM subsystem reflects interactions between array physics, command legality, scheduler policy, PHY margin, and reliability controls before software experiences final latency or bandwidth.

Model row lifecycle constraints explicitly: ACT-to-CAS >= tRCD, ACT-to-PRE >= tRAS, PRE-to-next-ACT >= tRP, and ACT-to-next-ACT(same bank) >= tRC while coordinating neighboring-bank limits via tRRD/tFAW. DRAM inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing. as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as Timing budget worksheet and assertion set for tRCD, tRP, tRAS, tRC, tRRD, and tFAW checks across random and stress traffic..

JEDEC timing is the exposed face of underlying analog settle and power-window constraints. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

Review discipline should enforce a single causal chain: traffic pattern -> command-level behavior -> array/PHY effect -> measured product impact. That chain prevents tuning folklore from replacing evidence.