DRAM & Memory Design · All levels

tRCD / tRP / tRAS / tRC Timing: Interview Drills

Interview Drills for tRCD / tRP / tRAS / tRC Timing.

Interview drills

Interview Drills for tRCD / tRP / tRAS / tRC Timing focuses on Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing.. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

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PROMPT
You observe Meet core row timing inequalities with no row-cycle violations: tRCD before column access, tRAS minimum row active time, tRP precharge restore, and tRC row reuse spacing. on tRCD / tRP / tRAS / tRC Timing. Explain root cause and release decision.

STRONG ANSWER
1. Defines failing traffic context and first transition loss.
2. Explains mechanism: Model row lifecycle constraints explicitly: ACT-to-CAS >= tRCD, ACT-to-PRE >= tRAS, PRE-to-next-ACT >= tRP, and ACT-to-next-ACT(same bank) >= tRC while coordinating neighboring-bank limits via tRRD/tFAW.
3. Requests proving artifact: Timing budget worksheet and assertion set for tRCD, tRP, tRAS, tRC, tRRD, and tFAW checks across random and stress traffic.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic DDR tuning ideas without command evidence, owner accountability, or risk controls.

Interview evidence matrix

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DRAM EVIDENCE MATRIX - tRCD / tRP / tRAS / tRC Timing

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| row-hit/miss + ACT/PRE mix    | locality and row-state cost    | lane-level capture integrity   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| JEDEC legality + bus timeline | timing-window pressure         | root cause by itself           | correlate with traffic map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot addresses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

DRAM deep dive

Timing closure requires command scheduling that respects tRCD/tRP/tRAS/tFAW windows under bursty traffic.

Concept diagram

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COMMAND TIMING SEQUENCE

ACT -> tRCD -> READ/WRITE -> tRAS(min) -> PRE -> tRP -> next ACT

Metric graph

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TIMING LOSS DRIVERS

read/write turnarounds  ██████
tFAW throttling         ████
guardband padding       ███

Reports and artifacts

timing-parameter budget table
command-bus utilization timeline
tFAW window violation log
read/write turnaround penalty report

Mini case study

A firmware timing preset favored stability but overpadded turnaround timing, reducing sustained throughput during mixed traffic.

Debug branches

Audit command spacing against JEDEC minimums and guards
Track bus-direction switches and hidden dead cycles
Validate timing updates on both average and p99 latency

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this DRAM topic is closed under real traffic?

Key takeaways

Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing DRAM captures.

Common pitfalls

Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.

Interview answer expansion

Strong interview answers for tRCD / tRP / tRAS / tRC Timing start with workload framing and metric framing, then explain mechanism plainly: Model row lifecycle constraints explicitly: ACT-to-CAS >= tRCD, ACT-to-PRE >= tRAS, PRE-to-next-ACT >= tRP, and ACT-to-next-ACT(same bank) >= tRC while coordinating neighboring-bank limits via tRRD/tFAW.

Then propose a measurement plan: command legality, row-hit dynamics, turnaround cost, refresh interference, and PHY margin where relevant.

Finally, present one bounded fix plus regression risk. DRAM interviews reward explicit tradeoff ownership, not generic tuning slogans.

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