SystemVerilog Assertions (SVA)

Section goal

SVA converts intent into executable properties so simulation and formal runs catch temporal bugs early, document protocol contracts, and accelerate debug with cycle-accurate failure traces.

How to study this section

1. Start with each topic hub and restate the requirement intent in your own words.

2. Use reports and debug pages to classify first divergence accurately.

3. Practice worked examples and interview drills with fixed run metadata.

4. Close with checklist and residual-risk framing before signoff claims.

Topics

1. sva-sequences-and-properties/ - SVA Sequences and Properties

2. implication-and-clocking/ - Implication Operators, Clocking, and Reset Gating

3. liveness-vs-safety/ - Safety vs Liveness, Strong vs Weak

4. assertion-debug/ - Debugging Failing Assertions Effectively

Related topics

• Formal Verification course hub

Formal deep dive

SVA scales when temporal intent, clock sampling, and reset gating are precise enough to be replayed and reviewed.

Concept diagram

SVA INTENT CHAIN

timing contract -> sequence composition -> property implication -> sampled failure trace

Metric graph

ASSERTION QUALITY SIGNALS

non-vacuous hit rate    ████████
clock/reset mismatches  ████
false-positive churn    ███

Metrics and artifacts to collect

• assertion trigger hit-rate

• implication timing mismatch bucket

• reset-window noise ratio

• assertion decomposition quality score

Mini case study

A protocol failure vanished after correcting `|->` vs `|=>` semantics and reset masking boundaries.

Debug branches

• Confirm antecedent trigger at sampled clock edges.

• Verify implication operator matches protocol timing contract.

• Split monolithic properties into stage-local checks.

Senior review question

Ask: which requirement intent is proven, under which assumptions, and what residual risk remains?