Formal Verification · All levels

Debugging Failing Assertions Effectively

SystemVerilog Assertions (SVA): Debug starts by classifying failure type: antecedent misuse, vacuity, sampling mismatch, reset masking, or real RTL bug.

What this topic teaches

Debugging Failing Assertions Effectively converts formal concepts into release-ready verification decisions. Debug starts by classifying failure type: antecedent misuse, vacuity, sampling mismatch, reset masking, or real RTL bug.

Senior-engineer framing question

When non-vacuous closure rate, counterexample turnaround, and residual-risk trend by requirement class regresses, can you isolate the first failing assumption/property boundary, prove causality, assign owner, and close with auditable risk?

diagram
FORMAL EXECUTION FLOW - Debugging Failing Assertions Effectively

requirement intent and risk class
      |
      v
property and assumption modeling
      |
      v
proof engine exploration and trace extraction
      |
      v
counterexample classification and fix hypothesis
      |
      v
re-proof, coverage audit, and signoff decision

Evidence to collect

  • Primary metric: non-vacuous closure rate, counterexample turnaround, and residual-risk trend by requirement class.

  • Primary artifact: closure packet for Debugging Failing Assertions Effectively: assumptions audit, proof status matrix, and replay-ready divergence trace.

  • Owners to include: formal verification owner, rtl owner, SystemVerilog Assertions (SVA) owner.

  • One reproducible failing trace and one stable comparator run.

  • One fixed metadata run with assumptions and tool settings locked.

Ownership layers

diagram
OWNERSHIP LAYERS - Debugging Failing Assertions Effectively

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| formal verification owner | property and model integrity      | assumptions and proof packet   |
| rtl owner | implementation root-cause closure | RTL fix and replay evidence    |
| SystemVerilog Assertions (SVA) owner | signoff governance and rollout    | risk memo + acceptance gates   |
+----------------------+--------------------------------+--------------------------------+

Decision matrix

diagram
EVIDENCE MATRIX - Debugging Failing Assertions Effectively

+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                    | Tells you                      | Does not prove                 | Next action               |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| property status by class    | closure shape by requirement   | model realism                  | pair with cover reachability |
| vacuity and trigger checks  | assertion meaningfulness       | full legal-path exploration    | inspect assumptions       |
| counterexample traces       | concrete divergence path       | complete bug-space closure     | classify and replay       |
| assumption audit trail      | model boundary confidence      | implementation correctness     | review spec traceability  |
| before/after trend packet   | mitigation movement quality    | long-window stability          | run broader matrix        |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+

Key takeaways

  • Start with first-divergence classification before broad model edits.

  • Tie each claim to one proving artifact and one owner action.

  • Close with residual-risk statement and rollback-safe criteria.

Common pitfalls

  • Treating green status as correctness without vacuity and reachability audits.

  • Changing assumptions and RTL together, destroying causality.

  • Declaring closure without replaying representative legal scenarios.

Formal deep dive

SVA scales when temporal intent, clock sampling, and reset gating are precise enough to be replayed and reviewed.

Concept diagram

diagram
SVA INTENT CHAIN

timing contract -> sequence composition -> property implication -> sampled failure trace

Metric graph

diagram
ASSERTION QUALITY SIGNALS

non-vacuous hit rate    ████████
clock/reset mismatches  ████
false-positive churn    ███

Metrics and artifacts to collect

  • assertion trigger hit-rate

  • implication timing mismatch bucket

  • reset-window noise ratio

  • assertion decomposition quality score

Mini case study

A protocol failure vanished after correcting `|->` vs `|=>` semantics and reset masking boundaries.

Debug branches

  • Confirm antecedent trigger at sampled clock edges.

  • Verify implication operator matches protocol timing contract.

  • Split monolithic properties into stage-local checks.

Senior review question

Ask: which requirement intent is proven, under which assumptions, and what residual risk remains?

Key takeaways

  • Tie each proof claim to assumption boundaries and reachability evidence.

  • Prefer minimal reversible fixes and preserve legal behavior visibility.

Common pitfalls

  • Treating runtime reduction as proof-quality improvement without audits.

  • Declaring closure while critical covers remain unreachable.

  • Using broad waivers instead of first-divergence root-cause ownership.