SVA Sequences and Properties: Mechanism

Mechanism to understand

Mechanism for SVA Sequences and Properties is anchored on non-vacuous closure rate, counterexample turnaround, and residual-risk trend by requirement class. Convert outcomes into assumption-aware, evidence-backed actions.

A `sequence` captures a timed pattern and a `property` turns that pattern into a check under a sampling clock.

• Name the first boundary where requirement intent diverges.

• Prove mechanism with one high-confidence evidence packet.

• Assign owner for smallest reversible mitigation.

Execution flow

FORMAL EXECUTION FLOW - SVA Sequences and Properties

requirement intent and risk class
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      v
property and assumption modeling
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      v
proof engine exploration and trace extraction
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      v
counterexample classification and fix hypothesis
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      v
re-proof, coverage audit, and signoff decision

Formal deep dive

SVA scales when temporal intent, clock sampling, and reset gating are precise enough to be replayed and reviewed.

Concept diagram

SVA INTENT CHAIN

timing contract -> sequence composition -> property implication -> sampled failure trace

Metric graph

ASSERTION QUALITY SIGNALS

non-vacuous hit rate    ████████
clock/reset mismatches  ████
false-positive churn    ███

Metrics and artifacts to collect

• assertion trigger hit-rate

• implication timing mismatch bucket

• reset-window noise ratio

• assertion decomposition quality score

Mini case study

A protocol failure vanished after correcting `|->` vs `|=>` semantics and reset masking boundaries.

Debug branches

• Confirm antecedent trigger at sampled clock edges.

• Verify implication operator matches protocol timing contract.

• Split monolithic properties into stage-local checks.

Senior review question

Ask: which requirement intent is proven, under which assumptions, and what residual risk remains?

Key takeaways

• Tie each proof claim to assumption boundaries and reachability evidence.

• Prefer minimal reversible fixes and preserve legal behavior visibility.

Common pitfalls

• Treating runtime reduction as proof-quality improvement without audits.

• Declaring closure while critical covers remain unreachable.

• Using broad waivers instead of first-divergence root-cause ownership.

Mechanism deep dive

Mechanism detail: A `sequence` captures a timed pattern and a `property` turns that pattern into a check under a sampling clock. Example: `sequence req_gnt; req ##[1:3] gnt; endsequence` matches grant arrival 1 to 3 cycles after request, while `property p_req_gnt; @(posedge clk) disable iff (!rst_n) req |-> ##[1:3] gnt; endproperty` enforces it only when reset is inactive. Use exact delay (`##2`), ranged delay (`##[1:3]`), and repetition (`sig[*3]`, `sig[->1]`) deliberately because each choice changes what traces are legal. Keep sequence intent narrow and compose larger properties from smaller sequences to avoid unreadable monolithic assertions.

Prefer requirement decomposition over monolithic assertions for debug clarity.