Course map
- 6 lessons
Starts with The Debug Loop
- 8 lessons
Starts with Determinism and Seeds
- 9 lessons
Starts with Reading a Waveform with a Question
- 10 lessons
Starts with The First Wrong Cycle
- 6 lessons
Starts with A Hypothesis Must Predict
- 16 lessons
Starts with Logic Bugs: Off-by-One, Width and Sign
- 9 lessons
Starts with RTL Simulation
- 7 lessons
Starts with Hang, Livelock or Starvation
- 7 lessons
Starts with Why Intermittents Happen
- 7 lessons
Starts with Fix the Cause, Not the Symptom
- 12 lessons
Starts with The Off-by-One That Fails at Wrap
- 5 lessons
Starts with Triage Meetings That Converge
- 5 lessons
Starts with Find the Bug in This Waveform
About this course
Pick a path. Each one orders the same lessons for a different goal. Your progress counts on every path.
New RTL or DV engineers.
6 steps · 51 lessons · about 10 h of reading
- Part 0 · What Debugging Is
- Part 1 · Reproduce
- Part 2 · Observe
- Part 3 · Localise
- Part 4 · Hypothesise and Test
- Part 10 · Case Studies
At the end you can: reproduce, observe and localise any failure in your own block without guessing, then try it on real hunts.
Who this course is for
Anyone who designs or verifies hardware and spends more time debugging than they would like: from your first month on the job to leading a team. Each lesson carries a level badge, Foundation (F), Working (W), Senior (S) or Principal (P), and ends with a lens for the levels above it.
The method in one picture
Show how the course is organised
Every part of the course zooms into one or two steps of this loop. Every case study walks the whole loop and marks the step where the hunt was won or lost.
Real failures, not stories
Every failure in this course is a real run: Icarus Verilog, Verilator, Yosys with a formal solver, and git, on code shown on the page. Most of them happen in dbglab, a small system with a bus, a DMA engine, FIFOs, a CSR block and a power gate, whose version history contains real bugs for you to find.