Low Power Verification · All levels
Power-Gating Controller and PMU FSM Verification
Dynamic Power & Gating: Power-gating controller verification focuses on PMU FSM correctness through every entry, retention, isolation, shutoff, restore, and re-enable path, including rare abort and fault branches. The sequencing contract is strict: isolate before power-off, retain before context loss, clamp crossings while source is invalid, and de-isolate only after supply/clock/reset readiness criteria are met. Verification should include temporal assertions for handshake ordering with regulators, clock controllers, reset controllers, and software-visible status registers, plus scoreboards that confirm context integrity after repeated sleep-wake cycling. Stress campaigns must inject asynchronous wake requests, overlapping subsystem dependencies, timeout/retry events, and partial-failure cases to prove FSM robustness under realistic platform orchestration. Formal or semi-formal checks are especially effective for invariants such as mutually exclusive illegal states, eventual completion from non-fault commands, and guaranteed safe fallback behavior when an external acknowledgment never arrives.
What this topic teaches
Power-Gating Controller and PMU FSM Verification converts LPV concepts into staff-level verification decisions. Power-gating controller verification focuses on PMU FSM correctness through every entry, retention, isolation, shutoff, restore, and re-enable path, including rare abort and fault branches. The sequencing contract is strict: isolate before power-off, retain before context loss, clamp crossings while source is invalid, and de-isolate only after supply/clock/reset readiness criteria are met. Verification should include temporal assertions for handshake ordering with regulators, clock controllers, reset controllers, and software-visible status registers, plus scoreboards that confirm context integrity after repeated sleep-wake cycling. Stress campaigns must inject asynchronous wake requests, overlapping subsystem dependencies, timeout/retry events, and partial-failure cases to prove FSM robustness under realistic platform orchestration. Formal or semi-formal checks are especially effective for invariants such as mutually exclusive illegal states, eventual completion from non-fault commands, and guaranteed safe fallback behavior when an external acknowledgment never arrives.
Senior-engineer framing question
When illegal transition rate, corruption incidence, and deterministic replay quality under low-power scenarios regresses, can you isolate first failing low-power boundary, prove it with artifacts, assign owners, and close with rollback-safe validation?
LOW-POWER VERIFICATION FLOW - Power-Gating Controller and PMU FSM Verification
power intent and mode definitions
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v
domain controls and transition sequencing
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v
simulation behavior (isolation, retention, corruption)
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v
assertions and coverage evidence
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v
triage, bounded fix, and signoff closureEvidence to collect
Primary metric: illegal transition rate, corruption incidence, and deterministic replay quality under low-power scenarios.
Primary artifact: evidence packet for Power-Gating Controller and PMU FSM Verification: transition timeline, assertions, and before-after replay summary.
Owners to include: LPV lead, power-intent owner, Dynamic Power & Gating owner.
One reproducible failing scenario and one stable comparator run.
One fixed metadata run with branch and configuration tags locked.
Ownership layers
OWNERSHIP LAYERS - Power-Gating Controller and PMU FSM Verification
+----------------------+--------------------------------+--------------------------------+
| Team | Primary responsibility | Closure artifact |
+----------------------+--------------------------------+--------------------------------+
| LPV lead | scenario intent and closure | review rationale memo |
| power-intent owner | transition and boundary contract | timeline + assertion packet |
| Dynamic Power & Gating owner | regression signoff readiness | validation matrix + risk note |
+----------------------+--------------------------------+--------------------------------+Decision matrix
EVIDENCE MATRIX - Power-Gating Controller and PMU FSM Verification
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| transition timeline traces | first failing LP phase | complete root-cause ownership | correlate with intent map |
| UPF-aware assertion logs | contract violations by phase | silicon product impact | map to scenario severity |
| corruption/X classification | actionable vs noisy failures | legal transition completeness | replay key mode corners |
| save/restore snapshots | state integrity movement | isolation correctness | pair with crossing checks |
| before-after regressions | mitigation movement quality | long-tail stability | run full matrix |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+Key takeaways
Start with transition-boundary classification before broad methodology changes.
Tie each LPV claim to one proving artifact and one owner action.
Close with validation matrix and rollback trigger for signoff safety.
Common pitfalls
Waiving failures before first-failure boundary classification.
Changing intent, RTL, and checkers in one step and losing causality.
Declaring closure on local runs without broader replay coverage.
Low-power verification deep dive
Dynamic power control verification must preserve correctness while validating meaningful efficiency gains.
Concept diagram
DYNAMIC POWER CONTROL
policy intent -> gating/DVFS action -> functional safety checks -> efficiency evidenceMetric graph
DYNAMIC CONTROL SIGNALS
unsafe transitions ████
power savings gain ███████
control-loop noise ███Metrics and artifacts to collect
clock-gating safety matrix
activity and toggle intent correlation
DVFS transition stability report
PMU controller state-machine coverage
Mini case study
A DVFS optimization regressed reliability until transition checks included concurrent interrupt and wake conditions.
Debug branches
Prove functional safety before claiming power benefit.
Correlate activity reduction with expected policy behavior.
Stress PMU control loops under asynchronous events.
Senior review question
Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?
Key takeaways
Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.
Common pitfalls
Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.