Low Power Verification · All levels

Power-Gating Controller and PMU FSM Verification: Debug Playbook

Debug Playbook for Power-Gating Controller and PMU FSM Verification.

Debug playbook

Debug Playbook for Power-Gating Controller and PMU FSM Verification is anchored on illegal transition rate, corruption incidence, and deterministic replay quality under low-power scenarios. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Dynamic Power & Gating / Power-Gating Controller and PMU FSM Verification

1. Symptom
   - Failing metric: illegal transition rate, corruption incidence, and deterministic replay quality under low-power scenarios
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: Power-gating controller verification focuses on PMU FSM correctness through every entry, retention, isolation, shutoff, restore, and re-enable path, including rare abort and fault branches. The sequencing contract is strict: isolate before power-off, retain before context loss, clamp crossings while source is invalid, and de-isolate only after supply/clock/reset readiness criteria are met. Verification should include temporal assertions for handshake ordering with regulators, clock controllers, reset controllers, and software-visible status registers, plus scoreboards that confirm context integrity after repeated sleep-wake cycling. Stress campaigns must inject asynchronous wake requests, overlapping subsystem dependencies, timeout/retry events, and partial-failure cases to prove FSM robustness under realistic platform orchestration. Formal or semi-formal checks are especially effective for invariants such as mutually exclusive illegal states, eventual completion from non-fault commands, and guaranteed safe fallback behavior when an external acknowledgment never arrives.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: evidence packet for Power-Gating Controller and PMU FSM Verification: transition timeline, assertions, and before-after replay summary
   - Required owners: LPV lead, power-intent owner, Dynamic Power & Gating owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Dynamic power control verification must preserve correctness while validating meaningful efficiency gains.

Concept diagram

diagram

DYNAMIC POWER CONTROL

policy intent -> gating/DVFS action -> functional safety checks -> efficiency evidence

Metric graph

diagram

DYNAMIC CONTROL SIGNALS

unsafe transitions      ████
power savings gain      ███████
control-loop noise      ███

Metrics and artifacts to collect

clock-gating safety matrix
activity and toggle intent correlation
DVFS transition stability report
PMU controller state-machine coverage

Mini case study

A DVFS optimization regressed reliability until transition checks included concurrent interrupt and wake conditions.

Debug branches

Prove functional safety before claiming power benefit.
Correlate activity reduction with expected policy behavior.
Stress PMU control loops under asynchronous events.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

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