Low Power Verification · All levels

Isolation + Level-Shifter Placement Bugs at Domain Crossings: Debug Playbook

Debug Playbook for Isolation + Level-Shifter Placement Bugs at Domain Crossings.

Debug playbook

Debug Playbook for Isolation + Level-Shifter Placement Bugs at Domain Crossings is anchored on Placement legality violations found pre-tapeout and post-route crossing ECO count caused by incorrect iso/LS ordering.. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Isolation & Level Shifting / Isolation + Level-Shifter Placement Bugs at Domain Crossings

1. Symptom
   - Failing metric: Placement legality violations found pre-tapeout and post-route crossing ECO count caused by incorrect iso/LS ordering.
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: A frequent silicon escape comes from physically legal but functionally unsafe placement of isolation and level shifters around domain boundaries. If a path needs both cells, ordering matters: placing a level shifter before isolation can expose the sink to uncontrolled values during source collapse, while placing isolation in a domain that powers off with its source can nullify protection entirely. Verification should correlate logical intent with physical instance location, checking that isolation cells reside in an alive domain (or use always-on rails), level shifters are located where the library characterizes them for voltage reliability, and compound crossings satisfy required iso-then-shift or shift-then-iso policy as defined by architecture. Cross-probing static low-power reports with post-route connectivity and power-grid annotations is essential to catch cases where ECO moves or auto-insertion altered intended ordering.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: Domain-boundary crossing audit combining netlist topology, placement region legality, and required iso/LS ordering checks.
   - Required owners: physical design lead, low-power methodology owner, UPF signoff owner, STA and reliability owner, backend integration manager
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Boundary correctness depends on timing: isolate and shift at the right crossings and right phases.

Concept diagram

diagram

BOUNDARY SAFETY VIEW

domain crossing -> level-shift requirement -> isolation control -> OFF/ON transition behavior

Metric graph

diagram

BOUNDARY BUG CLASSES

missing isolation      █████
late isolation         ████
LS misdirection        ███

Metrics and artifacts to collect

cross-domain boundary inventory
clamp-value correctness report
LS direction and threshold checks
missing or redundant boundary action list

Mini case study

A boundary bug escaped unit tests until domain-off traffic stress revealed late isolation enable timing.

Debug branches

Map each crossing to expected LS and isolation behavior.
Verify enable timing against collapse and restore edges.
Check clamp safety for protocol-facing signals.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

Practice this lesson