Low Power Verification · All levels
Isolation Strategy and Clamp Value Verification: Debug Playbook
Debug Playbook for Isolation Strategy and Clamp Value Verification.
Debug playbook
Debug Playbook for Isolation Strategy and Clamp Value Verification is anchored on Escaped X-propagation defects per regression and percentage of UPF isolation strategies proven with mode-aware assertion coverage.. Convert observations into mechanism-backed and owner-bound actions.
Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.
Review memo template
LPV REVIEW MEMO - Isolation & Level Shifting / Isolation Strategy and Clamp Value Verification
1. Symptom
- Failing metric: Escaped X-propagation defects per regression and percentage of UPF isolation strategies proven with mode-aware assertion coverage.
- Trigger context: <seed/mode/sequence>
- First failing phase: <entry/off/exit/boundary>
2. Mechanism hypothesis
- Candidate mechanism: Isolation verification starts by proving that every crossing from a switchable source domain into an always-on or differently powered sink has a valid strategy for all legal power states. Beyond checking strategy existence, the core risk is clamp semantics: control signals may require clamp-to-0 for safe disable, while status or handshake paths may require clamp-to-1 to avoid false wakeups or stuck protocol states. Robust verification binds power-state-aware assertions to confirm isolation enable timing relative to power-off sequencing, ensures clamp values align with functional safety intent, and validates behavior through reset, retention restore, and power cycling corners. Simulation and formal should both detect windows where rails collapse before isolation asserts, because even short windows can corrupt downstream state or trigger latent protocol deadlocks.
- Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
- Missing evidence: <trace/assertion/report>
3. Proposed action
- Smallest reversible change: <intent/RTL/checker/flow>
- Expected movement: <failure trend/replay stability>
- Regression risk: compatibility, coverage, signoff delay
4. Signoff
- Required artifact: Isolation intent-to-implementation matrix mapping each domain crossing to strategy rule, clamp value rationale, and power-state assertion set.
- Required owners: low-power architecture owner, UPF/CPF integration owner, RTL design owner, power-aware verification lead, signoff quality owner
- Final decision: ship, bounded rollout, rollback, or escalateLow-power verification deep dive
Boundary correctness depends on timing: isolate and shift at the right crossings and right phases.
Concept diagram
BOUNDARY SAFETY VIEW
domain crossing -> level-shift requirement -> isolation control -> OFF/ON transition behaviorMetric graph
BOUNDARY BUG CLASSES
missing isolation █████
late isolation ████
LS misdirection ███Metrics and artifacts to collect
cross-domain boundary inventory
clamp-value correctness report
LS direction and threshold checks
missing or redundant boundary action list
Mini case study
A boundary bug escaped unit tests until domain-off traffic stress revealed late isolation enable timing.
Debug branches
Map each crossing to expected LS and isolation behavior.
Verify enable timing against collapse and restore edges.
Check clamp safety for protocol-facing signals.
Senior review question
Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?
Key takeaways
Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.
Common pitfalls
Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.
Debug ladder
Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.
Avoid mixed fixes before first-principles classification.