Low Power Verification · All levels

Power Mode Sequencing and Handshake Robustness: Debug Playbook

Debug Playbook for Power Mode Sequencing and Handshake Robustness.

Debug playbook

Debug Playbook for Power Mode Sequencing and Handshake Robustness is anchored on Handshake completion success under stress, P99 entry/exit latency per mode, and number of sequencing deadlock or livelock scenarios proven absent.. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Power State Verification / Power Mode Sequencing and Handshake Robustness

1. Symptom
   - Failing metric: Handshake completion success under stress, P99 entry/exit latency per mode, and number of sequencing deadlock or livelock scenarios proven absent.
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: Mode sequencing spans hardware and software: requests originate from firmware policy engines, propagate through PMU state machines, and require acknowledgments from clocks, resets, retention controllers, and fabric quiesce logic before commitment. Verification must model this as a distributed transaction with explicit ownership of each handshake edge, including retries, abort paths, and timeout escalation when one participant stalls. Corner cases often involve partial progress (for example retention saved but clock gate denied) where rollback semantics are underspecified; tests and assertions should confirm whether the system safely returns to the previous mode or completes a controlled forward recovery without exposing mixed-domain visibility. Sequencing robustness also requires stress across asynchronous events such as interrupts, debug halts, thermal throttling, and watchdog resets, ensuring these events cannot reorder handshake phases in ways that momentarily violate isolation, reset containment, or coherency expectations.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: Mode-entry/exit sequence map with handshake ownership table, rollback policy, and timeout escalation playbook.
   - Required owners: PMU microarchitecture owner, firmware power management lead, clock and reset design owner, verification lead, system validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram

PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram

STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

PST legality matrix
illegal transition histogram
entry/exit handshake coverage
mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

Validate legal state graph first.
Stress concurrent control events and asynchronous wakeups.
Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

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