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Low Power Verification · All levels

Power Mode Sequencing and Handshake Robustness: Theory Deep Dive

Theory Deep Dive for Power Mode Sequencing and Handshake Robustness.

Foundational theory

Power Mode Sequencing and Handshake Robustness is core to Power State Verification. Treat each power behavior change as a correctness and signoff risk decision.

Core concepts explained

  • Mode sequencing spans hardware and software: requests originate from firmware policy engines, propagate through PMU state machines, and require acknowledgments from clocks, resets, retention controllers, and fabric quiesce logic before commitment. Verification must model this as a distributed transaction with explicit ownership of each handshake edge, including retries, abort paths, and timeout escalation when one participant stalls. Corner cases often involve partial progress (for example retention saved but clock gate denied) where rollback semantics are underspecified; tests and assertions should confirm whether the system safely returns to the previous mode or completes a controlled forward recovery without exposing mixed-domain visibility. Sequencing robustness also requires stress across asynchronous events such as interrupts, debug halts, thermal throttling, and watchdog resets, ensuring these events cannot reorder handshake phases in ways that momentarily violate isolation, reset containment, or coherency expectations.

  • Primary metric: Handshake completion success under stress, P99 entry/exit latency per mode, and number of sequencing deadlock or livelock scenarios proven absent.

  • Primary artifact: Mode-entry/exit sequence map with handshake ownership table, rollback policy, and timeout escalation playbook.

  • Owners: PMU microarchitecture owner, firmware power management lead, clock and reset design owner, verification lead, system validation owner

  • Power intent and RTL behavior must stay aligned through transitions

  • Proof quality beats broad waive strategies in low-power closure

Why this matters in low-power signoff

Power-state verification is a protocol verification problem: legal transitions, ordering contracts, and corner-case concurrency. Teams that enforce this reduce false alarms and real escapes.

Mental model

diagram
POWER STATE TABLE

State     CORE   GPU   RET   ISO   VALID EXIT
--------  -----  ----  ----  ----  -----------------------------
ON        ON     ON    OFF   OFF   normal operation
IDLE      ON     CLK-G OFF   OFF   activity drops below threshold
SLEEP     OFF    OFF   ON    ON    wake_event && restore_done
GPU-NAP   ON     OFF   OFF   ON    gpu_irq || host_request
DEEP-SLP  OFF    OFF   ON    ON    aon_timer || external_wakeup

Transition checks:
ON -> SLEEP: save -> isolate -> gate clocks -> power off
SLEEP -> ON: power on -> wait stable -> restore -> de-isolate

Worked intuition

  1. Classify symptom first: illegal transition, corruption, isolation break, retention drift, or X-prop ambiguity.

  2. Pinpoint first phase boundary where expected low-power behavior diverges.

  3. Quantify movement in Handshake completion success under stress, P99 entry/exit latency per mode, and number of sequencing deadlock or livelock scenarios proven absent. before broad refactors.

  4. Collect Mode-entry/exit sequence map with handshake ownership table, rollback policy, and timeout escalation playbook. with fixed run metadata and mode sequencing.

  5. Apply one bounded fix and replay both targeted and broader scenarios.

  6. Publish owner-signed closure note with rollback trigger.

Common misconceptions

  • Passing nominal ON/OFF smoke proves transition correctness.

  • UPF compile clean means all intent semantics are correct.

  • All X-prop failures indicate real product escapes.

  • Retention behavior can be trusted without multi-cycle restore stress.

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram
PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram
STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

  • PST legality matrix

  • illegal transition histogram

  • entry/exit handshake coverage

  • mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

  • Validate legal state graph first.

  • Stress concurrent control events and asynchronous wakeups.

  • Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

  • Tie each LPV claim to a concrete transition boundary and one proving artifact.

  • Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

  • Treating power-aware failures as random before boundary classification.

  • Waiving X-prop failures before proving impact and root cause.

  • Declaring closure without deterministic replay across key modes.

Theory reinforcement

Theory matters when it predicts concrete failure signatures and closure boundaries.

Translate LPV semantics into reproducible verification outcomes.

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