Power State Tables (PST) and UPF Intent Consistency

What this topic teaches

Power State Tables (PST) and UPF Intent Consistency converts LPV concepts into staff-level verification decisions. Power state tables define the legal combinations of domain supplies, isolation intent, retention expectations, and always-on dependencies, but real bugs appear when equivalent state names map to different electrical assumptions across UPF, RTL, and firmware. Verification must treat PST as an executable contract: each state declaration is cross-checked against switch controls, clamp polarity, retention save/restore windows, and clock/reset prerequisites before simulation even starts. During dynamic runs, monitors should reconstruct effective domain state from actual control signals and compare it against the declared PST tuple, including intermediate settle windows where supply ramps, isolation asserts, and reset deassert order can temporarily violate assumptions. A robust flow also validates forbidden composite states that are not directly requested by software but can emerge from asynchronous updates or watchdog recovery paths, because those illegal combinations often create silent corruption rather than immediate protocol failures.

Senior-engineer framing question

When PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic. regresses, can you isolate first failing low-power boundary, prove it with artifacts, assign owners, and close with rollback-safe validation?

LOW-POWER VERIFICATION FLOW - Power State Tables (PST) and UPF Intent Consistency

power intent and mode definitions
      |
      v
domain controls and transition sequencing
      |
      v
simulation behavior (isolation, retention, corruption)
      |
      v
assertions and coverage evidence
      |
      v
triage, bounded fix, and signoff closure

Evidence to collect

• Primary metric: PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic..

• Primary artifact: PST intent traceability matrix linking UPF states to RTL control points, firmware enums, and per-state assertion bundles..

• Owners to include: low-power architecture owner, UPF and implementation lead, DV low-power methodology owner, firmware power manager owner, post-silicon validation owner.

• One reproducible failing scenario and one stable comparator run.

• One fixed metadata run with branch and configuration tags locked.

Ownership layers

OWNERSHIP LAYERS - Power State Tables (PST) and UPF Intent Consistency

+----------------------+--------------------------------+--------------------------------+
| Team                 | Primary responsibility         | Closure artifact               |
+----------------------+--------------------------------+--------------------------------+
| low-power architecture owner | scenario intent and closure      | review rationale memo          |
| UPF and implementation lead | transition and boundary contract | timeline + assertion packet    |
| DV low-power methodology owner | regression signoff readiness     | validation matrix + risk note  |
+----------------------+--------------------------------+--------------------------------+

Decision matrix

EVIDENCE MATRIX - Power State Tables (PST) and UPF Intent Consistency

+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                    | Tells you                      | Does not prove                 | Next action               |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+
| transition timeline traces  | first failing LP phase         | complete root-cause ownership  | correlate with intent map |
| UPF-aware assertion logs    | contract violations by phase   | silicon product impact         | map to scenario severity  |
| corruption/X classification | actionable vs noisy failures   | legal transition completeness  | replay key mode corners   |
| save/restore snapshots      | state integrity movement       | isolation correctness          | pair with crossing checks |
| before-after regressions    | mitigation movement quality    | long-tail stability            | run full matrix           |
+-----------------------------+--------------------------------+--------------------------------+---------------------------+

Key takeaways

• Start with transition-boundary classification before broad methodology changes.

• Tie each LPV claim to one proving artifact and one owner action.

• Close with validation matrix and rollback trigger for signoff safety.

Common pitfalls

• Waiving failures before first-failure boundary classification.

• Changing intent, RTL, and checkers in one step and losing causality.

• Declaring closure on local runs without broader replay coverage.

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

• PST legality matrix

• illegal transition histogram

• entry/exit handshake coverage

• mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

• Validate legal state graph first.

• Stress concurrent control events and asynchronous wakeups.

• Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

• Tie each LPV claim to a concrete transition boundary and one proving artifact.

• Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

• Treating power-aware failures as random before boundary classification.

• Waiving X-prop failures before proving impact and root cause.

• Declaring closure without deterministic replay across key modes.