Low Power Verification · All levels

Power State Tables (PST) and UPF Intent Consistency: Expanded Case Study

Expanded Case Study for Power State Tables (PST) and UPF Intent Consistency.

Extended case study

A regression tied to Power State Tables (PST) and UPF Intent Consistency appears after power-intent or PMU sequence updates.

Background

Previous baseline was stable. New low-power behavior improved one mode but introduced unstable corner behavior in transition-heavy tests.

Symptoms observed

  • PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic. worsens under stressed transition sequences

  • same testcase can pass in functional mode but fail in power-aware mode

  • teams disagree whether issue is intent, RTL, firmware, or checker noise

Investigation timeline

  1. Hour 0: freeze test seed, intent revision, RTL commit, and PMU configuration tags.

  2. Hour 1: collect transition timeline and assertion failures around first symptom.

  3. Hour 2: classify failure mode and narrow candidate boundaries.

  4. Hour 3: create smallest reproducer with explicit phase and crossing visibility.

  5. Hour 4: apply one reversible fix and rerun focused LPV tests.

  6. Hour 5: run broader regression subset for blast-radius confidence.

  7. Hour 6: publish closure packet and update guardrail checks.

Root cause

Root cause traced to Power State Tables (PST) and UPF Intent Consistency: Power state tables define the legal combinations of domain supplies, isolation intent, retention expectations, and always-on dependencies, but real bugs appear when equivalent state names map to different electrical assumptions across UPF, RTL, and firmware.

Fix and validation

  • Make transition and control ownership explicit at the failing boundary.

  • Add one targeted checker or assertion for recurring failure signature.

  • Prove fix with before-after artifacts under fixed mode sequencing.

Lessons learned

  • Treat low-power boundaries as protocol contracts, not optional hints.

  • Prefer bounded fixes over multi-axis edits during triage.

  • Convert each escaped bug class into a lasting guardrail.

diagram
CASE STUDY - Power State Tables (PST) and UPF Intent Consistency
escape risk / debug latency / closure confidence trend

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram
PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram
STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

  • PST legality matrix

  • illegal transition histogram

  • entry/exit handshake coverage

  • mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

  • Validate legal state graph first.

  • Stress concurrent control events and asynchronous wakeups.

  • Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

  • Tie each LPV claim to a concrete transition boundary and one proving artifact.

  • Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

  • Treating power-aware failures as random before boundary classification.

  • Waiving X-prop failures before proving impact and root cause.

  • Declaring closure without deterministic replay across key modes.

Principal LPV review addendum

Power State Tables (PST) and UPF Intent Consistency should be reviewed as a transition integrity system, not just isolated checks.

Use PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic. as alarm and PST intent traceability matrix linking UPF states to RTL control points, firmware enums, and per-state assertion bundles. as proof.

Power-state verification is a protocol verification problem: legal transitions, ordering contracts, and corner-case concurrency. Closure quality comes from reproducible evidence and explicit owners.