Low Power Verification · All levels

Power State Tables (PST) and UPF Intent Consistency: Debug Playbook

Debug Playbook for Power State Tables (PST) and UPF Intent Consistency.

Debug playbook

Debug Playbook for Power State Tables (PST) and UPF Intent Consistency is anchored on PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic.. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Power State Verification / Power State Tables (PST) and UPF Intent Consistency

1. Symptom
   - Failing metric: PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic.
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: Power state tables define the legal combinations of domain supplies, isolation intent, retention expectations, and always-on dependencies, but real bugs appear when equivalent state names map to different electrical assumptions across UPF, RTL, and firmware. Verification must treat PST as an executable contract: each state declaration is cross-checked against switch controls, clamp polarity, retention save/restore windows, and clock/reset prerequisites before simulation even starts. During dynamic runs, monitors should reconstruct effective domain state from actual control signals and compare it against the declared PST tuple, including intermediate settle windows where supply ramps, isolation asserts, and reset deassert order can temporarily violate assumptions. A robust flow also validates forbidden composite states that are not directly requested by software but can emerge from asynchronous updates or watchdog recovery paths, because those illegal combinations often create silent corruption rather than immediate protocol failures.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: PST intent traceability matrix linking UPF states to RTL control points, firmware enums, and per-state assertion bundles.
   - Required owners: low-power architecture owner, UPF and implementation lead, DV low-power methodology owner, firmware power manager owner, post-silicon validation owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram

PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram

STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

PST legality matrix
illegal transition histogram
entry/exit handshake coverage
mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

Validate legal state graph first.
Stress concurrent control events and asynchronous wakeups.
Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

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