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Low Power Verification · All levels

Power State Tables (PST) and UPF Intent Consistency: Theory Deep Dive

Theory Deep Dive for Power State Tables (PST) and UPF Intent Consistency.

Foundational theory

Power State Tables (PST) and UPF Intent Consistency is core to Power State Verification. Treat each power behavior change as a correctness and signoff risk decision.

Core concepts explained

  • Power state tables define the legal combinations of domain supplies, isolation intent, retention expectations, and always-on dependencies, but real bugs appear when equivalent state names map to different electrical assumptions across UPF, RTL, and firmware. Verification must treat PST as an executable contract: each state declaration is cross-checked against switch controls, clamp polarity, retention save/restore windows, and clock/reset prerequisites before simulation even starts. During dynamic runs, monitors should reconstruct effective domain state from actual control signals and compare it against the declared PST tuple, including intermediate settle windows where supply ramps, isolation asserts, and reset deassert order can temporarily violate assumptions. A robust flow also validates forbidden composite states that are not directly requested by software but can emerge from asynchronous updates or watchdog recovery paths, because those illegal combinations often create silent corruption rather than immediate protocol failures.

  • Primary metric: PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic.

  • Primary artifact: PST intent traceability matrix linking UPF states to RTL control points, firmware enums, and per-state assertion bundles.

  • Owners: low-power architecture owner, UPF and implementation lead, DV low-power methodology owner, firmware power manager owner, post-silicon validation owner

  • Power intent and RTL behavior must stay aligned through transitions

  • Proof quality beats broad waive strategies in low-power closure

Why this matters in low-power signoff

PST correctness controls whether every mode transition is legal-by-construction; weak PST reasoning creates hidden protocol holes.

Mental model

diagram
POWER STATE TABLE

State     CORE   GPU   RET   ISO   VALID EXIT
--------  -----  ----  ----  ----  -----------------------------
ON        ON     ON    OFF   OFF   normal operation
IDLE      ON     CLK-G OFF   OFF   activity drops below threshold
SLEEP     OFF    OFF   ON    ON    wake_event && restore_done
GPU-NAP   ON     OFF   OFF   ON    gpu_irq || host_request
DEEP-SLP  OFF    OFF   ON    ON    aon_timer || external_wakeup

Transition checks:
ON -> SLEEP: save -> isolate -> gate clocks -> power off
SLEEP -> ON: power on -> wait stable -> restore -> de-isolate

Worked intuition

  1. Classify symptom first: illegal transition, corruption, isolation break, retention drift, or X-prop ambiguity.

  2. Pinpoint first phase boundary where expected low-power behavior diverges.

  3. Quantify movement in PST legality closure (allowed states vs observed states) and count of state-encoding mismatches between UPF, firmware tables, and RTL control logic. before broad refactors.

  4. Collect PST intent traceability matrix linking UPF states to RTL control points, firmware enums, and per-state assertion bundles. with fixed run metadata and mode sequencing.

  5. Apply one bounded fix and replay both targeted and broader scenarios.

  6. Publish owner-signed closure note with rollback trigger.

Common misconceptions

  • Passing nominal ON/OFF smoke proves transition correctness.

  • UPF compile clean means all intent semantics are correct.

  • All X-prop failures indicate real product escapes.

  • Retention behavior can be trusted without multi-cycle restore stress.

Low-power verification deep dive

Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.

Concept diagram

diagram
PST CONTROL LOOP

state request -> legality check -> handshake sequencing -> mode entry -> monitored exit

Metric graph

diagram
STATE RISK MIX

illegal transitions     ██████
sequence race bugs      █████
stable mode paths       ████████

Metrics and artifacts to collect

  • PST legality matrix

  • illegal transition histogram

  • entry/exit handshake coverage

  • mode sequencing anomaly log

Mini case study

A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.

Debug branches

  • Validate legal state graph first.

  • Stress concurrent control events and asynchronous wakeups.

  • Bind fixes to explicit transition and owner contracts.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

  • Tie each LPV claim to a concrete transition boundary and one proving artifact.

  • Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

  • Treating power-aware failures as random before boundary classification.

  • Waiving X-prop failures before proving impact and root cause.

  • Declaring closure without deterministic replay across key modes.

Theory reinforcement

Theory matters when it predicts concrete failure signatures and closure boundaries.

Translate LPV semantics into reproducible verification outcomes.

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