Low Power Verification · All levels
Legal and Illegal PST Transition Checks: Inputs and Outputs
Inputs and Outputs for Legal and Illegal PST Transition Checks.
Inputs and outputs contract
Inputs and Outputs for Legal and Illegal PST Transition Checks is anchored on Illegal transition escape rate, transition-checker latency to first error, and percentage of legal arcs exercised with pass/fail evidence.. Convert observations into mechanism-backed and owner-bound actions.
INPUTS
- power-mode sequence and ownership context
- seed, order, and configuration metadata
- intent assumptions for transitions and crossings
- assertion and coverage expectation envelope
OUTPUTS
- evidence-backed failure classification
- owner-signed mitigation proposal
- validation matrix and rollback triggers
- release recommendationOwnership split
OWNERSHIP LAYERS - Legal and Illegal PST Transition Checks
+----------------------+--------------------------------+--------------------------------+
| Team | Primary responsibility | Closure artifact |
+----------------------+--------------------------------+--------------------------------+
| DV assertion owner | scenario intent and closure | review rationale memo |
| power controller RTL lead | transition and boundary contract | timeline + assertion packet |
| firmware sequencing owner | regression signoff readiness | validation matrix + risk note |
+----------------------+--------------------------------+--------------------------------+Low-power verification deep dive
Power-state correctness is a protocol contract: legal transitions, robust sequencing, and safe concurrent event handling.
Concept diagram
PST CONTROL LOOP
state request -> legality check -> handshake sequencing -> mode entry -> monitored exitMetric graph
STATE RISK MIX
illegal transitions ██████
sequence race bugs █████
stable mode paths ████████Metrics and artifacts to collect
PST legality matrix
illegal transition histogram
entry/exit handshake coverage
mode sequencing anomaly log
Mini case study
A sporadic low-power failure closed only after proving a wake-versus-thermal race in PMU transition sequencing.
Debug branches
Validate legal state graph first.
Stress concurrent control events and asynchronous wakeups.
Bind fixes to explicit transition and owner contracts.
Senior review question
Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?
Key takeaways
Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.
Common pitfalls
Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.
Handoff explanation
Inputs should include mode sequence, domain status, and control ownership context.
Outputs should include deterministic reproducer and acceptance boundaries.