Community Projects

Automated RTL to GDSII flow built on top of several open source tools including OpenROAD.

Platform for sharing IP cores and hardware designs with the open source community.

Package manager and build tool for HDL code and libraries.

Hardware description language written in Scala for generating VHDL/Verilog RTL.

Community-maintained collection of open source RISC-V processor implementations.

Coroutine-based cosimulation testbench environment for verifying VHDL/Verilog RTL.