Digital Design/Combinational & Sequential

Combinational & Sequential Logic

Master the fundamentals of digital logic design from basic gates to complex sequential circuits.

🎯 Fundamental Concepts

Combinational Logic Circuits

Beginner

Logic circuits where outputs depend only on current inputs, with no memory elements.

Key Topics:

•Logic gates (AND, OR, NOT, NAND, NOR, XOR)
•Truth tables and logic expressions
•Multiplexers and demultiplexers
•Encoders and decoders
•Adders and arithmetic circuits

Truth Table:

A | B | AND | OR | XOR | NAND
--|---|-----|----|----|-----
0 | 0 |  0  | 0  | 0  |  1
0 | 1 |  0  | 1  | 1  |  1  
1 | 0 |  0  | 1  | 1  |  1
1 | 1 |  1  | 1  | 0  |  0

Verilog Example:

// 4-to-1 Multiplexer
module mux_4to1 (
  input  logic [3:0] data_in,
  input  logic [1:0] select,
  output logic data_out
);

always_comb begin
  case (select)
    2'b00: data_out = data_in[0];
    2'b01: data_out = data_in[1];
    2'b10: data_out = data_in[2];
    2'b11: data_out = data_in[3];
  endcase
end

endmodule

Sequential Logic Circuits

Intermediate

Circuits with memory elements where outputs depend on both inputs and previous state.

Key Topics:

•Flip-flops (D, JK, T, SR types)
•Latches vs flip-flops
•Counters (binary, ring, Johnson)
•Shift registers
•State machines and memory

Truth Table:

D FF | Clk | Q(next)
-----|-----|--------
  0  | ↑   |   0
  1  | ↑   |   1
  X  | 0/1 | Q(prev)

Verilog Example:

// 4-bit Counter with Load
module counter_4bit (
  input  logic clk, rst_n,
  input  logic load, enable,
  input  logic [3:0] load_data,
  output logic [3:0] count
);

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    count <= 4'b0000;
  else if (load)
    count <= load_data;
  else if (enable)
    count <= count + 1;
end

endmodule

Arithmetic Circuits

Intermediate

Digital circuits performing mathematical operations like addition, subtraction, and multiplication.

Key Topics:

•Binary addition and subtraction
•Half adder and full adder
•Ripple carry vs carry lookahead
•Multipliers (array, Booth)
•ALU design principles

Truth Table:

Full Adder
A | B | Cin | Sum | Cout
--|---|-----|-----|-----
0 | 0 |  0  |  0  |  0
0 | 0 |  1  |  1  |  0
0 | 1 |  0  |  1  |  0
1 | 1 |  1  |  1  |  1

Verilog Example:

// 4-bit Ripple Carry Adder
module ripple_carry_adder_4bit (
  input  logic [3:0] a, b,
  input  logic cin,
  output logic [3:0] sum,
  output logic cout
);

logic [2:0] carry;

// Full adder instances
full_adder fa0 (.a(a[0]), .b(b[0]), .cin(cin),     .sum(sum[0]), .cout(carry[0]));
full_adder fa1 (.a(a[1]), .b(b[1]), .cin(carry[0]), .sum(sum[1]), .cout(carry[1]));
full_adder fa2 (.a(a[2]), .b(b[2]), .cin(carry[1]), .sum(sum[2]), .cout(carry[2]));
full_adder fa3 (.a(a[3]), .b(b[3]), .cin(carry[2]), .sum(sum[3]), .cout(cout));

endmodule

// Full Adder Module
module full_adder (
  input  logic a, b, cin,
  output logic sum, cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));

endmodule

🏗️ Common Design Examples

Traffic Light Controller

SequentialMedium

FSM-based traffic light system with timing control

Inputs:

clk

reset

sensor

Outputs:

red

yellow

green

8-bit ALU

CombinationalHigh

Arithmetic Logic Unit with multiple operations

Inputs:

a[7:0]

b[7:0]

opcode[2:0]

Outputs:

result[7:0]

zero

carry

Frequency Divider

SequentialMedium

Clock frequency division by programmable factor

Inputs:

clk_in

reset

div_factor[3:0]

Outputs:

clk_out

Priority Encoder

CombinationalLow

8-to-3 priority encoder with valid output

Inputs:

data_in[7:0]

Outputs:

encoded[2:0]

valid

🛠️ Digital Design Tools

Logic Simulator

Simulate and verify digital logic circuits

Key Features:

✓Waveform viewing
✓Timing analysis
✓Test vectors
✓Coverage analysis

Popular Tools:

ModelSimVCSVivado Simulator

Logic Synthesis

Convert RTL to gate-level netlists

Key Features:

✓Technology mapping
✓Optimization
✓Timing constraints
✓Area/power trade-offs

Popular Tools:

Design CompilerGenusVivado Synthesis

Timing Analysis

Verify timing requirements and constraints

Key Features:

✓Setup/hold checking
✓Clock analysis
✓Critical paths
✓Slack reporting

Popular Tools:

PrimeTimeTempusVivado Timing

📚 Hands-On Tutorials

Beginner

Building Your First Counter

Step-by-step guide to designing a simple binary counter

Concepts Covered:

Flip-flopsClockResetEnable

⏱️ 20 mins

Intermediate

Designing a Simple ALU

Create an 8-bit ALU with basic arithmetic and logic operations

Concepts Covered:

AddersBoolean opsMultiplexersStatus flags

⏱️ 45 mins

Advanced

Advanced Sequential Circuits

Design complex counters and state machines

Concepts Covered:

State encodingMoore/MealyOptimizationHazards

⏱️ 60 mins

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