RTL Design — Complete Senior Prep Guide

Who this course is for

This is a complete RTL design curriculum from first principles through senior/staff-level topics. Each lesson includes extended theory, ASCII diagrams, multiple Verilog examples, waveform guides, interview angles, and hands-on exercises.

• Students and new grads entering VLSI/RTL roles

• Engineers moving from verification or firmware into design

• Interview prep for RTL/design positions (2–10 YOE)

• Anyone replacing ad-hoc notes with a structured reference

Course scale

The course contains 614 pages in a nested hub + sub-lesson structure. Most leaf lessons average 65+ content blocks (theory, code, charts, checklists).

Structure

rtl/                          course hub
rtl/<section>/                section hub (9 parts)
rtl/<section>/<topic>/        topic hub
rtl/<section>/<topic>/<sub>/  sub-lesson (core + supplemental)

Supplemental sub-lessons (per topic)

• Worked examples and waveforms

• Corner cases and stress tests

• Integration and sign-off notes

• Interview categories include advanced scenario + whiteboard drills

Cross-links (study paths)

High-value topic pairs to study together:

Related topics

• Pipelining ↔ STA intro

• Async FIFO ↔ CDC interview

• Synthesizable Verilog

• Senior interview hub

How to study

• Work parts in order; redo supplemental lessons after core subs

• Run every code example in simulation — reading is not enough

• Use interview model-answer chains for spaced repetition

• Estimated depth: 80–120 hours for full pass with labs