RTL Design/Reset & CDC Design

Reset & CDC Design

Master reset strategies, clock domain crossing techniques, and synchronization for reliable digital systems.

🎯 Essential Concepts

Reset Strategies

Fundamental

Different approaches to resetting digital systems reliably.

Key Topics:

•Synchronous vs asynchronous reset
•Reset assertion and deassertion
•Power-on reset circuits
•Reset synchronization
•Reset tree distribution

Implementation:

// Asynchronous reset, synchronous deassertion
module reset_sync (
  input  logic clk,
  input  logic async_rst_n,
  output logic sync_rst_n
);

logic [1:0] sync_reg;

always_ff @(posedge clk or negedge async_rst_n) begin
  if (!async_rst_n)
    sync_reg <= 2'b00;
  else
    sync_reg <= {sync_reg[0], 1'b1};
end

assign sync_rst_n = sync_reg[1];
endmodule

Clock Domain Crossing (CDC)

Advanced

Safe techniques for transferring data between different clock domains.

Key Topics:

•Metastability fundamentals
•Two-flop synchronizers
•Pulse synchronizers
•Handshake protocols
•Gray code techniques

Implementation:

// Handshake-based CDC
module handshake_cdc #(parameter WIDTH = 8) (
  // Source domain
  input  logic src_clk, src_rst_n,
  input  logic [WIDTH-1:0] src_data,
  input  logic src_valid,
  output logic src_ready,
  
  // Destination domain  
  input  logic dst_clk, dst_rst_n,
  output logic [WIDTH-1:0] dst_data,
  output logic dst_valid,
  input  logic dst_ready
);

// Source domain logic
logic src_req, src_ack_sync;
logic [WIDTH-1:0] data_reg;

always_ff @(posedge src_clk or negedge src_rst_n) begin
  if (!src_rst_n) begin
    src_req <= 1'b0;
    data_reg <= '0;
  end else if (src_valid && src_ready) begin
    src_req <= ~src_req;
    data_reg <= src_data;
  end
end

assign src_ready = (src_req == src_ack_sync);

// Destination domain logic
logic dst_req_sync, dst_ack;
logic dst_req_sync_d1;

always_ff @(posedge dst_clk or negedge dst_rst_n) begin
  if (!dst_rst_n) begin
    dst_req_sync_d1 <= 1'b0;
    dst_ack <= 1'b0;
  end else begin
    dst_req_sync_d1 <= dst_req_sync;
    if (dst_req_sync != dst_req_sync_d1)
      dst_ack <= dst_req_sync;
  end
end

assign dst_valid = (dst_req_sync != dst_req_sync_d1);
assign dst_data = data_reg;

// Synchronizers
sync_2ff u_req_sync (.clk(dst_clk), .rst_n(dst_rst_n), 
                     .async_in(src_req), .sync_out(dst_req_sync));
sync_2ff u_ack_sync (.clk(src_clk), .rst_n(src_rst_n), 
                     .async_in(dst_ack), .sync_out(src_ack_sync));
endmodule

Synchronizer Design

Intermediate

Building robust synchronizers to prevent metastability.

Key Topics:

•MTBF calculations
•Synchronizer depth selection
•Fast vs safe synchronizers
•Synchronizer failure modes
•Temperature and voltage effects

Implementation:

// Configurable depth synchronizer
module sync_nff #(
  parameter WIDTH = 1,
  parameter STAGES = 2,
  parameter RESET_VAL = 0
) (
  input  logic clk,
  input  logic rst_n,
  input  logic [WIDTH-1:0] async_in,
  output logic [WIDTH-1:0] sync_out
);

logic [WIDTH-1:0] sync_ff [STAGES];

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    for (int i = 0; i < STAGES; i++)
      sync_ff[i] <= RESET_VAL;
  end else begin
    sync_ff[0] <= async_in;
    for (int i = 1; i < STAGES; i++)
      sync_ff[i] <= sync_ff[i-1];
  end
end

assign sync_out = sync_ff[STAGES-1];

// Synthesis attributes to prevent optimization
(* ASYNC_REG = "TRUE" *) logic [WIDTH-1:0] sync_ff [STAGES];
endmodule

🔄 CDC Techniques Comparison

Two-Flop Synchronizer

Low ComplexityHigh MTBF

Use Case:

Single bit control signals

Pros:

+Simple
+Low latency
+Well understood

Cons:

-Single bit only
-Pulse can be lost

Gray Code Counter

Medium ComplexityVery High MTBF

Use Case:

Multi-bit counters/addresses

Pros:

+Multi-bit safe
+No decode errors
+Atomic updates

Cons:

-Counter values only
-Complex decode

Handshake Protocol

High ComplexityVery High MTBF

Use Case:

Data buses and control

Pros:

+Any data width
+No loss
+Flow control

Cons:

-Higher latency
-More complex
-More resources

Async FIFO

Very High ComplexityHigh MTBF

Use Case:

Data streaming

Pros:

+High throughput
+Buffering
+Rate adaptation

Cons:

-Most complex
-Higher power
-Area overhead

🔄 Reset Design Strategies

Synchronous Reset

Reset signal is synchronized to clock edge

Best for: Most digital logic

Advantages:

✓Timing predictable
✓No reset removal issues
✓Better for synthesis

Disadvantages:

✗Requires clock
✗Wider reset distribution
✗Power consumption

Asynchronous Reset

Reset takes effect immediately, independent of clock

Best for: Critical safety circuits

Advantages:

✓Works without clock
✓Immediate effect
✓Lower power

Disadvantages:

✗Reset removal issues
✗Metastability risk
✗Timing complexity

Mixed Reset

Asynchronous assertion, synchronous deassertion

Best for: High-performance systems

Advantages:

✓Best of both
✓Safe removal
✓Immediate assertion

Disadvantages:

✗More complex
✗Requires careful design
✗Additional logic

Review timing reports for CDC paths

Fix:

Add false path constraints

✅ CDC Design Checklist

Identify all clock domain boundariesCritical

Choose appropriate CDC techniqueCritical

Add proper synchronizers for control signalsCritical

Verify Gray code for counters

Check MTBF requirementsCritical

Add timing constraints for CDC pathsCritical

Verify reset synchronizationCritical

Review metastability protectionCritical

Validate with CDC tools

Ready to Master Reset & CDC Design?

Practice with real-world scenarios and learn advanced synchronization techniques for robust systems.

Practice CDC Problems Back to RTL Topics