Debug Interfaces & Observability

Section goal

Foundational bring-up debug interfaces and observability strategy spanning JTAG boundary scan, ARM SWD access paths, on-chip trace capture, and scan-dump based state visibility.

How to study this section

1. Start with each topic hub and restate first-failure boundaries in your own words.

2. Use reports and debug pages to separate symptoms from root-cause classes.

3. Practice worked examples and interview drills under fixed metadata.

4. Close with checklist and silicon impact before signoff claims.

Topics

1. jtag-and-boundary-scan/ - JTAG and IEEE 1149.1 Boundary Scan

2. swd-and-debug-access/ - ARM SWD and Debug Access Port

3. on-chip-trace/ - On-Chip Trace and Embedded Logic Analyzer

4. scan-dump-and-observability/ - Scan Dump for State Observability During Bring-Up

Related topics

• Silicon Bring-up course hub

Silicon bring-up deep dive

Debug interfaces are useful only when access paths are trusted, minimally intrusive, and synchronized to failure context.

Concept diagram

DEBUG ACCESS STACK

physical probes -> debug transport -> trace/scan capture -> correlated analysis

Metric graph

OBSERVABILITY MATURITY

access failures          ████
partial captures         █████
actionable captures      ███████

Metrics and artifacts to collect

• JTAG/SWD access success rate

• trace trigger hit coverage

• scan dump decode turnaround time

• observability gap backlog

Mini case study

A misdiagnosed silicon issue was cleared after TAP chain validation revealed a board-level debug domain assumption error.

Debug branches

• Validate access-layer prerequisites before deep protocol decode.

• Correlate trace timestamps with software checkpoints.

• Treat missing evidence as an observability gap, not closure.

Senior review question

Ask: what is the first failing boundary, which artifact proves it, and who owns bounded closure?