Transition Bins

Covering sequences, not values

Value bins prove a state was visited; transition bins prove a path was taken. The syntax bins b = (A => B) hits when consecutive samples of the coverpoint were A then B. Sequences chain: (A => B => C) needs three consecutive samples in that order. “Consecutive” means consecutive samples of the covergroup — which is why transition bins demand disciplined, every-relevant-moment sampling.

typedef enum logic [1:0] { IDLE, BUSY, DONE, ERR } st_e;

covergroup cg_fsm @(posedge clk);
  cp_arc : coverpoint state iff (rst_n) {
    // single transitions (FSM arcs)
    bins idle_busy = (IDLE => BUSY);
    bins busy_done = (BUSY => DONE);
    bins done_idle = (DONE => IDLE);
    bins any_err   = (IDLE, BUSY, DONE => ERR);  // set → value

    // multi-step path: full happy loop in one bin
    bins happy_loop = (IDLE => BUSY => DONE => IDLE);

    // multiple transitions in one bin (either counts)
    bins recover = (ERR => IDLE), (ERR => BUSY);
  }
endgroup

Repetition inside transitions

Two repetition operators compress repeated values. A [*N] means A for exactly N consecutive samples ([*2:4] gives a range). A [->N] is the nonconsecutive goto: N occurrences of A, with other values allowed in between, ending on the last A.

covergroup cg_seq @(posedge clk);
  cp_st : coverpoint state iff (rst_n) {
    // BUSY held exactly 3 cycles between IDLE and DONE:
    bins busy3      = (IDLE => BUSY [*3] => DONE);

    // BUSY held 2 to 4 cycles:
    bins busy_short = (IDLE => BUSY [*2:4] => DONE);

    // 2 non-consecutive ERR visits, then recovery to IDLE:
    bins flaky      = (ERR [->2] => IDLE);
  }
endgroup

SAMPLE STREAM:  IDLE BUSY BUSY BUSY DONE IDLE ...

  (IDLE => BUSY [*3] => DONE)
    IDLE ✓ → BUSY,BUSY,BUSY (3 consecutive) ✓ → DONE ✓  → BIN HIT

  SAMPLE STREAM:  ERR IDLE BUSY ERR IDLE ...

  (ERR [->2] => IDLE)
    ERR(1) ... ERR(2)  ← gaps allowed with [->]
    next sample IDLE ✓                            → BIN HIT

FSM transition coverage and the SVA boundary

The standard FSM recipe: one enum coverpoint for state occupancy (free named bins), plus one transition coverpoint enumerating every legal arc from the state diagram . Together they prove every state was reached and every designed edge was taken — which tool-extracted FSM code coverage approximates, but without your plan's naming or your knowledge of which arcs are architecturally interesting.

Know the limitations. Transition bins watch one coverpoint's consecutive samples — they cannot express relationships across multiple signals (“req rises, then within 3 cycles gnt while abort stayed low”), cannot tolerate arbitrary unrelated activity between steps the way temporal logic can, and missing one sample breaks the sequence silently. That territory belongs to cover property with SVA sequences. Rule of thumb: same variable, consecutive samples → transition bins; multiple signals or elastic timing → SVA cover.

• Transition bins reset on every covergroup sample mismatch — a missed sample (gated iff, skipped cycle) silently kills an in-flight sequence.

• Sampling per transaction instead of per cycle changes what “consecutive” means — design the trigger before the bins.

• Crosses of transition bins are not supported — cross applies to value bins.

• Interview angle: “FSM coverage — transition bins or SVA cover?” — answer with the single-variable vs multi-signal/elastic-timing boundary and you stand out.

Key takeaways

• bins (A => B) covers consecutive-sample transitions; chains express multi-step paths in one bin.

• [*N] repeats a value consecutively; [->N] counts nonconsecutive occurrences with gaps allowed.

• FSM coverage = enum coverpoint for states + transition coverpoint for every legal arc from the diagram.

• Transition bins are single-variable and gap-intolerant — multi-signal or elastic-timing sequences need SVA cover property.

Common pitfalls

• Sampling on transactions while bins assume cycles — “consecutive” no longer means what the bin says.

• An iff guard that skips samples mid-sequence — in-flight transitions silently abort, bins read zero.

• Enumerating illegal arcs as transition bins hoping for hits — use illegal_bins or an assertion to FLAG them instead.

• Trying to cover cross-signal handshakes with transition bins — wrong tool; that is SVA cover territory.