Every constraint, covergroup, and class library stands on the language core. Types, arrays, procedural scheduling, expressions, compilation, and interfaces form the substrate beneath them.
You need basic Verilog first: modules, assign, clocked always blocks and vectors. Start Here has a two-minute check. By the end of this part you can write a small self-checking testbench that uses the right types, containers and timing.
Topic | Lessons | What it covers | Time |
|---|---|---|---|
5 | How 4-state and 2-state types, nets, casting, and composite types fit together. | 40 min | |
4 | Four array families, when each one fits, and where to find every lesson. | 30 min | |
5 | Procedural code and scheduling: the always family, assignments, tasks, regions, startup and flow control. | 40 min | |
5 | Hub — signedness, equality flavors, unique/priority, shifts and streaming, and the width rules that silently corrupt results. | 40 min | |
5 | Packages, imports, compilation order, parameters and namespace rules for scalable testbenches. | 40 min | |
4 | Bundle bus signals into one port, add direction views, and sample and drive race-free. | 30 min |
logic bus that carries X into an int variable hide bugs?An int is 2-state and cannot represent X, so the unknown bits become 0. The checking code then compares a value that looks legal but is really unknown. Keep boundary signals 4-state and check for X explicitly before converting.