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Course contents

  • Start Here6
  • SystemVerilog Language Foundations35
    • SystemVerilog Data Types
    • Arrays: Packed, Dynamic, Queues & Associative
    • Procedural Code & Scheduling
      • always_comb, always_ff, always_latch
      • Blocking vs Nonblocking Assignments
      • Tasks vs Functions
      • The Event Scheduler & Stratified Regions
      • initial, final & Startup Ordering
      • Loops & Flow Control
    • Operators, Expressions & Width Rules
    • Packages, Typedefs & Compilation
    • Interfaces, Modports & Clocking Blocks
  • Object-Oriented SystemVerilog for Verification35
  • Constraint Randomization — Interview-Critical Deep Dive66
  • SystemVerilog Assertions — Interview-Critical Deep Dive63
  • Functional Coverage in SystemVerilog28
  • Testbench Architecture in SystemVerilog38
  • Advanced Language & Integration30
  • Senior & Interview Preparation34
  • Principal-Level Verification28
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‹SystemVerilog Language Foundations
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Language Foundations
  4. Procedural Code & Scheduling

Part 1 · Language Foundations · Intermediate

Procedural Code & Scheduling

Procedural code and scheduling: the always family, assignments, tasks, regions, startup and flow control.

  • 6topics
  • 6lessons

Topics in this section

  1. 1always_comb, always_ff, always_latch1 lesson
  2. 2Blocking vs Nonblocking Assignments1 lesson
  3. 3Tasks vs Functions1 lesson
  4. 4The Event Scheduler & Stratified Regions1 lesson
  5. 5initial, final & Startup Ordering1 lesson
  6. 6Loops & Flow Control1 lesson

Procedural code runs inside a discrete-event scheduler: at each simulation time it works through a fixed order of regions, and that order decides which value every statement sees.

This topic starts with the blocks and assignments you write every day, then opens the scheduler itself in The Event Scheduler.

Lesson

What it covers

always_comb, always_ff, always_latch

Intent contracts, sensitivity including functions, and the latch-inference fix.

Blocking vs Nonblocking Assignments

Two schedules, the swap classic, shift pipelines, and RTL and testbench rules.

Tasks vs Functions

The time rule, automatic storage, and argument directions including ref.

The Event Scheduler & Stratified Regions

Regions in one time slot, #0, $display versus $strobe, and deterministic startup.

Loops & Flow Control

Loop shapes, break, continue and disable, and timing controls in forever.

Check yourself A flop samples d at a clock edge while the testbench drives a new d with <= at the same edge. Which value does the flop take, and in which region does the drive commit?

The flop takes the pre-edge value. A nonblocking drive commits in the NBA region, after every Active-region sample has finished. A blocking = drive at that edge would be a race instead.

Interview

Scheduling questions are staples at every level: the two-register swap, what #0 really does, and why two initial blocks can race. Each lesson below carries one such question with its answer.

PreviousNext: always_comb, always_ff, always_latch

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Up nextalways_comb, always_ff, always_latch

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See also

  • SystemVerilog Data Types
  • Arrays: Packed, Dynamic, Queues & Associative
  • Operators, Expressions & Width Rules