SystemVerilog has four array families. Packed arrays are single bit vectors, fixed unpacked arrays are collections of elements, dynamic arrays and queues are sized at runtime, and associative arrays are sparse maps keyed by value.
Family | Declaration | Size | Synthesizable |
|---|---|---|---|
Packed |
| Fixed at compile time | Yes |
Unpacked fixed |
| Fixed at compile time | Yes |
Dynamic |
|
| No, testbench only |
Queue |
| Grows per push | No, testbench only |
Associative |
| One entry per written key | No, testbench only |
Lesson | You will build… |
|---|---|
Layout, slicing and copy rules that infer RAM instead of flops. | |
Runtime sizing plus an in-order checker built on a queue. | |
A sparse memory and an out-of-order checker keyed by ID. | |
Reductions, finders, sorting, and picking the right container. |
An associative array keyed by address. It allocates storage only for written keys. A fixed array of 2^64 bytes is impossible to allocate.