SystemVerilog Data Types

Overview

Every signal, transaction field, and loop counter you declare picks a position on two axes: 4-state vs 2-state (can it hold X and Z?) and net vs variable (is it resolved from drivers or assigned procedurally?). Getting those two choices right per context — RTL port, testbench class field, DPI argument — is what this topic teaches. Getting them wrong produces the classic failure modes: X bugs hidden by int, multiple-driver surprises on wire, and silent truncation at width boundaries.

The sub-lessons below move from value representation, through driver semantics and casting, into the debug skills (X tracing) and the composite types (enums, structs, unions, strings) that real testbenches are built from.

Sub-topics

1. 4-State vs 2-State Types — logic/reg/wire vs bit/byte/int, X/Z cost, initialization, where each belongs.

2. Nets vs Variables — drivers, resolution functions, multiple-driver rules, when logic replaces reg/wire.

3. Integer Types & Casting — the integer family, signedness, static cast vs $cast vs bit-stream cast, truncation.

4. X/Z Propagation & Pessimism — how X spreads, === vs ==, X in if/case, tracing X to its source.

5. Enums, Structs & Unions — enum methods, packed structs as bus payloads, packed vs unpacked, tagged unions.

6. Strings, Reals & Special Types — string methods, real math, chandle for DPI, event, $sformatf idioms.

Legend: [TYPE]

  DATA TYPE DECISION MAP [TYPE]

                 need X/Z modeling?
                 (RTL, DUT-facing)
                  │            │
                YES            NO (TB class internals)
                  │            │
        ┌─────────┴───┐    ┌───┴──────────────┐
        ▼             ▼    ▼                  ▼
   multiple        single  packed bits     numbers/handles
   drivers?        driver  bit [N-1:0]    int / byte / longint
        │             │                    string / real / chandle
       YES           NO
        │             │
        ▼             ▼
      wire          logic
   (resolved)    (var, one driver)

  Composite layer (either world):
    enum  → named states     struct → grouped fields
    union → shared storage   typedef → reusable names

Key takeaways

• Two axes decide every declaration: 4-state vs 2-state, and net vs variable.

• RTL and DUT-facing signals stay 4-state; class-based TB internals go 2-state for speed.

• Casting and the TB/RTL boundary are where X silently disappears — guard them explicitly.