SystemVerilog Data Types

Part 1 · Language Foundations · Intermediate

5topics
5lessons

Every declaration answers two questions: can this bit hold X or Z, and is its value resolved from drivers or stored. The five lessons below turn those answers into habits for ports, casts, and testbench types.

Two questions pick the type: must the value show X and Z, and how many things drive it.

Lesson	What it covers
4-State vs 2-State Types	X and Z modelling, the 2-state discount, the guarded boundary, and X tracing.
Nets vs Variables	Resolution against storage, one-driver logic, and buses that still need wires.
Integer Types & Casting	Widths, signedness, the three casts, and silent truncation rules.
Enums, Structs & Unions	Named states, shaped vectors, shared storage, and checked conversions.
Strings, Reals & Special Types	Dynamic text, testbench reals, opaque handles, and event sync.

Check yourself Testbench code copies a DUT bus into a 2-state variable and the checking code sees clean zeros. Where did the X go?

The 4-state to 2-state copy mapped X to 0 silently. The first lesson guards that boundary with an explicit unknown check before the copy.

Up next4-State vs 2-State Types

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