Operators, Expressions & Width Rules · SystemVerilog

Part 1 · Language Foundations · Intermediate

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5lessons

SystemVerilog expressions look like C but evaluate by their own rules. Signedness, operand width and X propagation follow the language reference manual, even when the result surprises.

Five rules cause most of the surprises: signedness, X in comparisons, checked case claims, shifts and packing, and the width an expression is computed at. Each lesson below takes one of them and proves it in simulation.

Lesson	What it proves
Signed and unsigned arithmetic	The compare bug, the `$signed` fix and the traps that poison a context.
Equality, case equality and wildcards	Which equality to use, why `casex` is banned and what replaces it.
unique, unique0 and priority	Checked branch claims that replaced the old synthesis pragmas.
Shifts, concatenation and streaming	Sign-preserving shifts, unsigned concats and one-line byte reversal.
Expression width and evaluation rules	The `(a+b)>>1` puzzle and the literal traps around it.

Check yourself A testbench must tell whether a bus bit is X. Which comparison can say so with a plain 1 or 0?

Case equality, ===. It compares X and Z literally and always returns 0 or 1, while == returns X when an X bit leaves the answer open. The equality lesson shows all three operators side by side.

Up nextSigned & Unsigned Arithmetic

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Lesson

What it proves

Signed and unsigned arithmetic

The compare bug, the $signed fix and the traps that poison a context.

Equality, case equality and wildcards

Which equality to use, why casex is banned and what replaces it.

unique, unique0 and priority

Checked branch claims that replaced the old synthesis pragmas.

Shifts, concatenation and streaming

Sign-preserving shifts, unsigned concats and one-line byte reversal.

Expression width and evaluation rules

The (a+b)>>1 puzzle and the literal traps around it.