Operators, Expressions & Width Rules

Overview

SystemVerilog expressions look like C but evaluate by their own rules. Signedness, operand width, and X-propagation are decided by the language reference manual, not by intuition — and the simulator follows the LRM even when the result surprises you. A comparison that mixes signed and unsigned operands silently becomes unsigned; an addition truncates to the width of its context; a casex happily matches X bits and hides a bus contention bug.

This topic builds the mental model that interviewers probe constantly: how the simulator decides the width and sign of every intermediate result, which equality operator to use where, and how unique/priority replaced the old synthesis pragmas. Master these rules once and an entire class of silent RTL and testbench bugs disappears.

Sub-topics

1. Signed & Unsigned Arithmetic — sign extension, expression poisoning, $signed/$unsigned casts.

2. Equality, Case Equality & Wildcards — == vs === vs ==?, casez/casex dangers, case inside.

3. unique, unique0 & priority — runtime-checked case/if qualifiers replacing full_case/parallel_case.

4. Shifts, Concatenation & Streaming — <<< on signed, reduction, replication, streaming pack/unpack.

5. Expression Width & Evaluation Rules — context vs self-determined width, the (a+b)>>1 puzzle.

OPERATORS & EXPRESSIONS TOPIC MAP

  every expression the simulator evaluates
              │
     ┌────────┼──────────────┬───────────────┐
     ▼        ▼              ▼               ▼
  SIGNEDNESS  EQUALITY     SHIFT/PACK     WIDTH RULES
  signed &    == === ==?   << <<< {}      context vs
  unsigned    casez/casex  {<<{}} {>>{}}  self-determined
     │        case inside     │               │
     │            │           │               │
     └─ one unsigned         reduction     truncation of
        operand poisons      & | ^ ~&      intermediate
        the whole expr           │         results
                                 │
              unique / priority qualifiers
              (runtime checks on case & if)

Key takeaways

• One unsigned operand makes the entire arithmetic context unsigned — the most common compare bug.

• Use == in RTL, === only in testbench X-checks, ==? / case inside for wildcard matching.

• Expression width is decided by context before evaluation — widen operands, not results.