Two schedules

A blocking assignment a = b updates the left side immediately, before the next statement runs. A nonblocking assignment a <= b evaluates the right side now, in the Active region, and commits the left side later, in the NBA region of the same slot.

That split models a flip-flop. Every clocked process samples pre-edge values and all updates commit together, so process execution order is irrelevant.

The swap and the shift register

Two registers exchange on a clock edge with no temporary: both right-hand sides sample before either update lands. With blocking assignments the first line destroys the value the second line needs, and both end up holding the old b.

The same principle pipelines data. Three nonblocking stages form a real 3-stage shift register; with blocking assignments the input would ripple through all three stages in one cycle.

Watch a against b, then q1 through q3. The pair exchanges every edge while 1s fill the pipe one stage per edge.

• Slot 0: a is 1 and b is 0 after the first exchange; q1 has the 1 while q2 and q3 are still 0.

• Slot 1: a is 0 and b is 1; the 1 reaches q2 while q3 is still 0.

• Slot 2: a is 1 and b is 0; the pipe reads 111 for the first time.

• Slot 3: a is 0 and b is 1; the pipe holds 111.

• Slot 4: a is 1 and b is 0; the pipe holds 111.

• Slot 5: a is 0 and b is 1; the pipe holds 111.

Rules for RTL and testbenches

The discipline follows from the semantics. Use nonblocking for every clocked element, blocking inside combinational blocks so intermediate values propagate in order, and never mix the two on the same variable.

Testbench sequencing defaults to blocking for its software-like order. Synchronous drives at a clock edge still use nonblocking, so the design samples old values exactly like a real upstream flop.

Testbench

The correct swap, its blocking collapse as a negative check, and the 3-stage pipe, all self-checked.

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module swap2 (
  input logic clk, rst,
  output logic a, b
);
  always_ff @(posedge clk) begin
    if (rst) begin a <= 1'b0; b <= 1'b1; end
    else begin
      a <= b;
      b <= a;
    end
  end
endmodule

module swap2_blocking (
  input logic clk, rst,
  output logic a, b
);
  always @(posedge clk) begin
    if (rst) begin a = 1'b0; b = 1'b1; end
    else begin
      a = b;
      b = a;
    end
  end
endmodule

module shift3 (
  input logic clk, rst,
  output logic q1, q2, q3
);
  always_ff @(posedge clk) begin
    if (rst) begin q1 <= 1'b0; q2 <= 1'b0; q3 <= 1'b0; end
    else begin
      q1 <= 1'b1;
      q2 <= q1;
      q3 <= q2;
    end
  end
endmodule

PASS: nonblocking swap exchanges each edge and the pipe fills 111 while blocking collapses

Related topics

• Next: Tasks vs Functions