Silicon Bring-up · All levels

JTAG and IEEE 1149.1 Boundary Scan: Debug Playbook

Debug Playbook for JTAG and IEEE 1149.1 Boundary Scan.

Debug playbook

Debug Playbook for JTAG and IEEE 1149.1 Boundary Scan is anchored on Board-level interconnect defect coverage, boundary-scan chain integrity rate, and mean time from first power-on to pin-level fault localization.. Convert observed behavior into mechanism-backed and owner-bound actions.

Freeze setup metadata and preserve first-failure state.
Locate first persistent boundary where behavior diverges.
Classify mechanism: dependency, margin, protocol, software, or silicon.
Apply one focused reproducer and one bounded fix.
Re-run replay, corner, and soak confidence matrix.

Review memo template

diagram

BRING-UP REVIEW MEMO - Debug Interfaces & Observability / JTAG and IEEE 1149.1 Boundary Scan

1. Symptom
   - Failing metric: Board-level interconnect defect coverage, boundary-scan chain integrity rate, and mean time from first power-on to pin-level fault localization.
   - Trigger context: <board/firmware/corner/test window>
   - First failing boundary: <power/reset/clock/interface/firmware>

2. Mechanism hypothesis
   - Candidate mechanism: IEEE 1149.1 boundary scan provides controllability and observability at package pins through an instruction register and per-pin boundary cells, enabling structural tests before full firmware bring-up is stable. In early silicon bring-up, teams use EXTEST, SAMPLE/PRELOAD, and BYPASS flows to verify solder connectivity, detect shorts/opens, and isolate board assembly defects without relying on internal functional clocks. Practical debug also depends on robust TAP state transitions, clean TCK/TMS signal quality, correct chain ordering across multiple devices, and reliable IDCODE discovery so test vectors map to the intended components. Boundary scan is most effective when integrated with board netlists and expected pin behavior tables, turning ambiguous boot failures into deterministic board-versus-silicon diagnosis.
   - Competing hypotheses: setup, dependency, margin, software path, silicon defect
   - Missing evidence: <trace/scope/register/report>

3. Proposed action
   - Smallest reversible change: <setup/script/config/firmware>
   - Expected movement: <repro rate/latency/pass trend>
   - Regression risk: stability, safety, release timeline, ownership handoff

4. Signoff
   - Required artifact: Boundary-scan bring-up pack with TAP chain map, mandatory instruction set checks, interconnect vector logs, and board net fault triage matrix.
   - Required owners: post-silicon bring-up owner, board design owner, DFT owner, manufacturing test owner
   - Final decision: ship, bounded rollout, rollback, respin escalation

Silicon bring-up deep dive

Debug interfaces are useful only when access paths are trusted, minimally intrusive, and synchronized to failure context.

Concept diagram

diagram

DEBUG ACCESS STACK

physical probes -> debug transport -> trace/scan capture -> correlated analysis

Metric graph

diagram

OBSERVABILITY MATURITY

access failures          ████
partial captures         █████
actionable captures      ███████

Metrics and artifacts to collect

JTAG/SWD access success rate
trace trigger hit coverage
scan dump decode turnaround time
observability gap backlog

Mini case study

A misdiagnosed silicon issue was cleared after TAP chain validation revealed a board-level debug domain assumption error.

Debug branches

Validate access-layer prerequisites before deep protocol decode.
Correlate trace timestamps with software checkpoints.
Treat missing evidence as an observability gap, not closure.

Senior review question

Ask: what is the first failing boundary, which artifact proves it, and who owns bounded closure?

Key takeaways

Tie every bring-up claim to one reproducible setup state and one proving artifact.
Prefer bounded fixes with clear owner and rollback trigger over broad multi-variable edits.

Common pitfalls

Running parallel uncontrolled experiments and losing causality.
Declaring closure without replaying across representative corners.
Escalating severity before bench/setup hypotheses are disproven.

Debug ladder

Sequence: reproduce -> classify -> isolate -> instrument -> bounded fix -> replay.

Avoid parallel broad edits before first root-cause class is proven.

Practice this lesson