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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
    • Connectivity Checking
    • Register (CSR) Verification
    • Deadlock, Livelock and Starvation Checks
    • Reset Determinism and X
    • Data, Handshake and Pipeline Property Sets
      • FIFO Ordering and Data Integrity
      • Handshake Bridge Properties
      • Pipeline Latency and Stall Properties
    • Other Applications, Honestly Scoped
  • Equivalence Checking14
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
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←Formal Applications
  1. Topics
  2. Formal Verification
  3. Formal Applications
  4. Data, Handshake and Pipeline Property Sets

Part 5 of 10Part 5 of 10/Formal ApplicationsAll levels

Data, Handshake and Pipeline Property Sets

Complete safety sets for the FIFO, the handshake stage and the pipeline: occupancy, integrity, conservation, stability and latency.

  • 3topics
  • 3lessons

Control proofs say the pointers are right; data proofs say the bytes are right. This topic writes the full safety set for each of the three datapath designs: occupancy, flags and pointer consistency plus a tracked-slot integrity property for the FIFO, stability and conservation plus tracked-word integrity for the handshake stage, and the three-cycle latency rule for the pipeline. Each set is proved whole, each mutant is killed by its named property, and the table in each lesson says which property catches which bug class.

Lesson

After it you can...

FIFO Ordering and Data Integrity

Prove occupancy, flags, pointers and slot integrity, and say what depth each needs.

Handshake Bridge Properties

Prove stability, conservation and integrity across backpressure.

Pipeline Latency and Stall Properties

Prove fixed latency with history registers and reuse the set for equivalence.

Suggested order: top to bottom. The FIFO set is the richest and introduces the tracked slot; the bridge set reuses the tracking idea on a skid; the pipeline set introduces input history, which the equivalence section reuses for its alignment argument. Prove each set at the depth its lesson states, and induction where the lesson shows the helper.

A top-down diagram. A design's safety set splits into control properties, which are counts, flags and pointers, and a data property, which follows one tracked slot or word. Both feed a box saying each mutant is killed by a named property.
A property set splits into control properties and one data property; the mutants show that each half catches bugs the other cannot.
Check yourself The control properties all pass but data corrupts in the system. Which property is missing?

The tracked-item integrity property: control counts words, only the tag check follows values. Add the tracked slot or word with its helper invariant, and mutate the data path to confirm it fails.

Related topics

  • SystemVerilog: FIFO Assertions

  • SystemVerilog: Valid-Ready Handshake

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See also

  • Connectivity Checking
  • Register (CSR) Verification
  • Deadlock, Livelock and Starvation Checks