Each lesson answers one part of one of the course's fifteen questions. It starts with a concrete problem, shows why the obvious answer fails, and builds the mechanism from there. Real protocols appear as evidence for the reasoning, never as the subject.
Block | What it is for |
|---|---|
Header | Level badge, the question the lesson answers, and what to read first |
Hook | A short scene that ends on the lesson's question |
The obvious answer, and why it breaks | The first idea most engineers have, and the case where it fails. The reasoning starts here. |
The idea and the picture | The mechanism, drawn on the course's sender, channel and receiver figure or as a sequence diagram |
Worked numbers | Sizing and overhead with numbers that add up. Numbers not taken from a specification are marked illustrative. |
Build it and watch it run | Runnable code and the real simulation waveform or model output it produces, read slot by slot |
Design space and how real protocols chose | The options, what each costs, and which protocols picked which, and why |
What breaks | A failure told as a short story: symptom, evidence, root cause, fix |
Senior or Principal lens | The second-order effect, or the question a design reviewer would ask |
Interview corner | The question as interviewers ask it, a weak answer, a strong answer, and follow-ups |
Check yourself, takeaways, next | Two or three scenario questions with reasoned answers, three lines to remember, and the problem the next lesson solves |
Badges F, W, S and P mark the lowest level a lesson serves: Foundation, Working, Senior, Principal. You do not need to skip lessons above your level, and senior readers should not skip foundation lessons: the lens at the end of each one is written for them.
DCLink (DenseChip Link) is a small point-to-point protocol that grows one idea at a time across the course. Each step is complete in its own lesson, so you can read any step without the earlier code.
Step | Part | What DCLink gains |
|---|---|---|
1 | 2 | Framing: a header, a payload, an end marker |
2 | 3 | valid/ready on one hop, then a skid buffer |
3 | 4 | Credit flow control over a pipelined wire |
4 | 5 | Read and write transactions with addresses, bursts and an error completion |
5 | 6 | Tags and four outstanding reads, completing out of order |
6 | 7 | One ordering rule and a fence |
7 | 8 | Two requesters and a round-robin arbiter |
8 | 9 | Separate request and response classes, removing a planted deadlock |
9 | 10 | CRC, sequence numbers and a replay buffer |
10 | 11 | A start-up handshake with capability exchange |
11 | 12 | An idle low-power state with a request/accept handshake |
12 | 15 | Assertions, a monitor and an ordering-aware scoreboard |
Every step follows one contract, so the steps agree with each other. A flit is 32 bits; a packet is one header flit and 0 to 15 payload flits. From step 4 the header is:
Bits | Field | Meaning |
|---|---|---|
31:28 |
| 0 WR, 1 RD, 2 CPL (completion), 3 FENCE, 4 TS1, 5 TS2 |
27:24 |
| WR and CPL: payload flits that follow. RD: no payload; |
23:22 |
| From step 5. Unique while its request is outstanding: at most one request per tag, so a completion matches exactly one request |
19:0 |
| WR and RD: flit address. CPL: 0 OK, 1 ERR |
What DCLink deliberately leaves out, so each step stays small: byte enables (it moves whole flits; lesson 5.9 shows what byte writes add), wrapping and fixed bursts, posted writes (every request gets exactly one CPL), and shared ordering IDs (lesson 6.4 contrasts its unique tags with AXI IDs). Each step's lesson shows only the signals that step needs.
Verilog and SystemVerilog listings are complete testbenches. They run in Icarus Verilog (iverilog -g2012 file.sv && vvp a.out) and Verilator (verilator --binary --timing file.sv), and print a line starting with PASS when their own checks succeed. The one exception, the assertion checker in lesson 15.3, needs Verilator and says so.
Python models use only the standard library. Run them with python3 file.py; they check their own results and print PASS.
Listings that start with // snippet are fragments, and // bad-example marks code shown as a mistake. Neither is meant to run.
Read the hook and stop. Try to answer the question before reading on.
After the obvious-answer section, predict the failure before the lesson describes it.
Read every waveform slot by slot against the "How to read it" list. This is the skill interviews test.
Answer the check-yourself questions out loud before opening them.
Once a part is done, try its drills page from memory.