Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
    • Valid-Only Streams
    • Wait States and Stretching
    • The Valid/Ready Handshake
    • The Valid/Ready Rules
    • Request/Acknowledge: Two-Phase and Four-Phase
    • Push and Pull
    • Global Stall or Elastic Pipeline
    • Register Slices
    • Skid Buffers
    • Bubbles and Half Throughput
    • Latency-Insensitive Design
    • Protocols Compared: Handshakes
    • Drills: Handshakes
  • Part 4: Flow Control17
  • Part 5: Transactions19
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
Loading lesson

‹First Principles of Hardware Protocols
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 3: Handshakes

Part 3 · Handshakes · All levels

Part 3: Handshakes

Is the receiver ready? Say exactly when a valid/ready transfer happens, and why both sides always agree.

  • 13topics
  • 13lessons
On this page

    Part 3 answers: Is the receiver ready?

    Where Part 3 sits among the fifteen questions of the course.

    Two blocks that run at different, varying rates have to agree, every cycle, on whether a piece of data moved. A handshake is that agreement. Get it wrong and words are lost, duplicated or corrupted, usually only under the one traffic pattern your tests did not try.

    This part starts with no backpressure at all, builds up to valid/ready and its rules, then covers request/acknowledge, register slices, skid buffers, the half-throughput trap and the theory of latency-insensitive design.

    After this part you can

    • Say exactly when a valid/ready transfer happens, and why both sides always agree.

    • Explain why a registered ready needs a two-entry skid buffer.

    • Spot the 50% throughput bug on a waveform.

    Warm-up: three questions from Part 2

    Answer each in your head before opening it. If two or more feel shaky, revisit Part 2: Encoding and Framing first.

    Check yourself Name two ways a receiver finds the end of a packet.

    Any two of: an explicit last flag (such as TLAST), a length field in the header, a unique delimiter symbol, a sync header that starts the next block, or a return to idle.

    Check yourself Why does bit stuffing add a bit after a run of identical bits?

    To guarantee transitions for clock recovery and to keep the run from looking like a reserved flag pattern.

    Check yourself What is the overhead of 8b/10b as a share of the line rate?

    20%: 2 of every 10 line bits carry no data.

    Lessons

    #

    Lesson

    Level

    Status

    3.1

    Valid-Only Streams

    F · Foundation

    Ready

    3.2

    Wait States and Stretching

    F · Foundation

    Ready

    3.3

    The Valid/Ready Handshake

    F · Foundation

    Ready

    3.4

    The Valid/Ready Rules

    W · Working

    Ready

    3.5

    Request/Acknowledge: Two-Phase and Four-Phase

    W · Working

    Ready

    3.6

    Push and Pull

    W · Working

    Ready

    3.7

    Global Stall or Elastic Pipeline

    W · Working

    Ready

    3.8

    Register Slices

    S · Senior

    Ready

    3.9

    Skid Buffers

    S · Senior

    Ready

    3.10

    Bubbles and Half Throughput

    S · Senior

    Ready

    3.11

    Latency-Insensitive Design

    P · Principal

    Ready

    —

    Protocols compared

    all levels

    Ready

    —

    Drills and checkpoint

    all levels

    Ready

    Every lesson in this part is ready. Work through them in order: each one sets up the problem the next one solves.

    Tip

    DCLink in this part. Steps 2a and 2b: valid/ready on one hop, then a skid buffer. DCLink is the small protocol you build across the course; see How to use this course.

    Where other courses go deeper

    This course teaches why protocols are designed the way they are. These lessons show how to build or sign off the same ideas, so this part links to them instead of repeating them.

    • RTL: Valid/Ready Handshake

    • RTL: Skid Buffer and Pipeline Stages

    • CDC & RDC: Handshake Protocols Across Domains

    Related topics

    • Course hub

    • Previous: Part 2 · Encoding and Framing

    • Next: Part 4 · Flow Control

    PreviousNext: Valid-Only Streams

    Up next

    Up nextValid-Only Streams

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • How to Use This Course
    • Reading Paths
    • Concept Map