Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Four levels carry two bits per symbol, halving the symbol rate for a given bit rate, but the level spacing drops to a third of NRZ's (about 9.5 dB), so the same noise causes more errors; PAM4 links rely on FEC.
TLAST marks the last transfer. On chip nothing is lost; on a cable one corrupted marker merges or splits packets with no recovery, so serial links use resynchronising framing and CRCs.
Type, address, length, a tag to match the response, requester identity for routing, and attributes; plus a sequence number and CRC at the link layer, with reserved bits for growth.
NRZI turns 0s into transitions, so the stuffed 0 guarantees a transition at least every seven bits for clock recovery, and keeps special patterns out of data. Worst-case overhead is about 17%.
On an AC-coupled link the received baseline drifts towards the data's recent average, pushing the threshold towards one level and raising errors even with good transitions.
To drop from 20% to about 1.5% overhead: Gen3 nearly doubled payload per lane (4 to about 7.9 Gb/s) with only a 1.6x line rate. Run length and balance then come from scrambling plus an always-transitioning 2-bit header.
No, only statistically; data equal to the scrambling sequence becomes constant. Sync headers stay unscrambled to guarantee a transition per block.
It hunts: slip one bit on each invalid header, require N valid headers in a row (false-lock chance about (½)ᴺ per wrong position), then tolerate a few bad headers per window while locked.
Task. Design the encoding and framing for a 4 Gb/s point-to-point serial link that is AC-coupled, carries variable-length packets of 8 to 256 bytes, and must recover quickly from bit errors. Justify each choice.
AC coupling and clock recovery need bounded runs and balance: at 4 Gb/s, 8b/10b's 20% overhead is acceptable and gives hard guarantees plus control symbols (a low-overhead header code with scrambling would also work, with statistical balance). Framing: start-of-packet and end-of-packet control symbols, so the receiver resynchronises at the next packet after an error, plus a length field in the header protected by a header CRC and a packet CRC trailer. Idle and alignment use control symbols (a comma for word alignment). If the link has two clock sources, add SKP-style filler for clock compensation.
A 0.
A length field.
It is computed over everything before it, so putting it last lets the sender stream the packet without buffering it.
25%: the stuffed bit can start a new run, so the worst data gets a stuff bit every four data bits.
By choosing, for each byte, between two code groups of opposite imbalance, whichever moves the running disparity back towards zero.
4 × 5 × 0.8 = 16 Gb/s.
Self-synchronising: each line error reappears once per tap.
Otherwise the FSM judges a word still at the old offset, finds it bad, and slips again, overshooting the right offset.
So a receiver acts only on several identical copies, never on a single corrupted one.
When traffic is packed into shared flits; with one message per flit, the largest flits are the least efficient at every size in the lesson's table.