A serial link never stops: even with nothing to send, the transmitter must keep sending something, or the receiver's clock recovery loses lock. Between packets the link must also carry alignment markers, filler for clock compensation, and messages used to train and manage the link. All of it shares the wire with data that can contain any bit pattern.
How does a link send information that can never be mistaken for data?
The obvious answer is a special byte value meaning "idle" or "start of packet". But data bytes can take every value, so any chosen value will sooner or later appear inside a payload and be misread. Escaping it (sending an escape byte first) works but makes length variable, the problem of lesson 2.4. A fast link wants control information that is unambiguous by construction, at fixed size, with no escaping.
Block codes create spare room. 8b/10b maps 256 byte values into 10-bit code groups, and there are far more valid 10-bit groups than needed, so some are reserved as control symbols (often called K-codes) that no data byte can produce. 64b/66b and 128b/130b create the same distinction with the 2-bit header: one value marks a data block, the other a control block (or ordered-set block) whose contents are interpreted as control.
Control symbols are then combined into short fixed sequences called ordered sets, each with a specific job:
Job | What the ordered set does | Lesson |
|---|---|---|
Idle | Fills the line between packets, keeping transitions and balance | 1.4 |
Alignment | Gives the receiver a pattern to find word, block or lane boundaries (for example the 8b/10b comma) | 1.5, 2.8 |
Clock compensation | Filler (SKP) the elastic buffer may delete or repeat | 1.7 |
Framing | Marks the start and end of packets | 2.2 |
Training and link management | Exchanges capabilities, speed and lane numbers during start-up; enters and leaves low-power states | 11.4, 12.4 |
A single control symbol could be enough to say "this is control". Ordered sets use several symbols for two reasons:
Robustness. A bit error can turn one symbol into another. Requiring a fixed sequence (and sending training sets repeatedly) lets the receiver reject a corrupted one instead of acting on it.
Information. Training ordered sets carry fields such as the lane number, supported speeds and requests. The leading control symbol says "this is an ordered set"; the rest carries the content.
Clock compensation adds one more twist: a SKP ordered set is made of a recognisable start followed by SKP symbols, so the receiver's elastic buffer can delete or add one SKP symbol and the set is still recognisable (lesson 1.7).
Approach | What it costs | When it wins |
|---|---|---|
Reserved code groups in a block code (8b/10b K-codes) | Overhead of the code itself | Unambiguous control at symbol granularity |
Header-marked control blocks (64b/66b, 128b/130b) | Control comes in whole blocks, which wastes space for small control messages | High-rate links where the code overhead must be low |
Escaped values in the data | Variable length, worst-case expansion | Low-rate byte-oriented links |
Separate sideband wires | Pins | On chip, or when pins are cheap |
Protocol | Control mechanism |
|---|---|
8b/10b links (PCIe Gen1–2, many others) | Reserved K-code control symbols that data cannot produce; K28.5 contains the comma used for word alignment. |
PCI Express Gen3–5 | A sync header of 01 marks an ordered-set block (10 marks data), used for training, SKP clock compensation and other link management. |
PCI Express (all generations) | SKP ordered sets for clock compensation; training ordered sets during link start-up. |
Ethernet | A preamble and start frame delimiter in front of every frame; 64b/66b links mark control blocks with header 10. |
A receiver acts on the first training ordered set it decodes, without waiting for a repeat (illustrative). A single bit error turns a lane-number field from 2 into 3, the receiver records the wrong lane order, and the link trains with two lanes swapped. Every packet then fails its CRC. Real training protocols send each ordered set many times and require several identical consecutive copies before acting, which is exactly what this receiver skipped.
There are many more valid 10-bit code groups than the 256 needed for data bytes, so some are reserved for control.
From its 2-bit sync header: 01 marks an ordered-set block, 10 a data block.
A single bit error can corrupt one copy; acting only on repeated identical copies prevents a corrupted field from changing the link's configuration.
Links send idle, alignment, filler, framing and training as control symbols or control blocks that data can never produce.
Block codes make this possible: spare code groups (8b/10b) or a header value that marks control (64b/66b, 128b/130b).
Ordered sets that change link state must be repeated and confirmed, because a corrupted one must never be half-applied.