Each protocol below had to decide how bits look on the wire and how a receiver finds where messages start and end. Read across for one protocol; read down to compare answers to one question.
Protocol | Line code | Transitions guaranteed by | Balance | Framing | Control information |
|---|---|---|---|---|---|
UART | NRZ | Start and stop bits each frame | Not needed (DC-coupled) | Idle, start bit, stop bit | None in-band |
I2C | Levels on SDA, clocked by SCL | Not needed: SCL is the clock | Not needed | START and STOP conditions (SDA changing while SCL high) | Address and acknowledge bits |
CAN | NRZ | Stuff bit after five identical bits | Not needed | Start of frame, identifier, fixed fields | Identifier and control fields |
USB 2.0 | NRZI | A stuffed 0 after six 1s | Not guaranteed | Sync pattern and end-of-packet marker | Packet identifiers |
AXI-Stream | On-chip levels | Not needed | Not needed | TLAST marks the last transfer | Side signals (TKEEP and others) |
Ethernet (frames) | Depends on the physical layer | Physical-layer code | Physical-layer code | Preamble and start frame delimiter; inter-frame gap | Type or length field; CRC-32 trailer |
10 Gb/s Ethernet (64b/66b) | NRZ | Sync header 01 or 10 on every block; scrambled payload | Statistical (scrambling) | Control blocks inside the block stream | Header 10 marks control blocks |
PCI Express Gen1–2 | NRZ | 8b/10b: at most five identical bits | Hard bound (running disparity) | Control symbols | K-codes; ordered sets (training, SKP) |
PCI Express Gen3–5 | NRZ | Sync header 10 or 01 on every 130-bit block; scrambled data | Statistical | Framing within data blocks | Header 01 marks ordered-set blocks |
PCI Express Gen6 | PAM4 | Physical-layer coding with FEC | Statistical | Fixed 256-byte flits | Flit structure: TLP bytes, data-link payload, CRC, FEC |
Slow links get guarantees cheaply with start bits or stuffing; fast links need fixed overhead, first 8b/10b, then low-overhead headers plus scrambling, then flits with FEC.
Balance only matters where the link is AC-coupled. Low-speed, DC-coupled protocols ignore it entirely.
On chip, framing is a wire. AXI-Stream needs only TLAST because nothing is lost between blocks; every off-chip protocol needs framing the receiver can resynchronise on.