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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding
    • Register Semantics
    • Combined and Split Transactions
    • Independent Channels
    • Posted and Non-Posted Writes
    • Bursts
    • Alignment, Strobes and Narrow Transfers
    • Boundary Rules
    • Width and Endianness Conversion
    • Transaction Attributes
    • Atomics
    • Sideband or In-Band
    • Interrupts and Notification
    • Descriptors, Rings and Doorbells
    • Bridges and Protocol Conversion
    • Protocols Compared: Transactions
    • Drills: Transactions
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
Loading lesson

‹First Principles of Hardware Protocols
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 5: Transactions

Part 5 · Transactions · All levels

Part 5: Transactions

What exactly is being asked? Explain why AXI splits reads and writes into separate channels.

  • 19topics
  • 19lessons
On this page

    Part 5 answers: What exactly is being asked?

    Where Part 5 sits among the fifteen questions of the course.

    Above flow control sits meaning: a read, a write, an address, a size, a response. The way a protocol describes a transaction decides how much concurrency it allows, what can go wrong, and what software can rely on.

    This part covers reads versus writes, address maps and decode errors, register semantics, split transactions, independent channels, posted writes, bursts, byte enables, boundary rules, conversion, attributes, atomics, interrupts, descriptor rings and bridges.

    After this part you can

    • Explain why AXI splits reads and writes into separate channels.

    • Compute the beat addresses and byte enables of any burst.

    • Say what an AXI-to-APB bridge cannot carry across.

    Warm-up: three questions from Part 4

    Answer each in your head before opening it. If two or more feel shaky, revisit Part 4: Flow Control first.

    Check yourself What does a credit stand for?

    One free buffer slot at the receiver. The sender spends one to send and gets it back when the receiver frees the slot.

    Check yourself How big must a receiver buffer be for full throughput under credit flow control?

    At least bandwidth × credit round-trip time; at one flit per cycle, at least as many flits as the round trip has cycles.

    Check yourself What is head-of-line blocking?

    A stalled item at the front of a shared queue blocks items behind it that could otherwise proceed.

    Lessons

    #

    Lesson

    Level

    Status

    5.1

    Reads and Writes Are Not Symmetric

    F · Foundation

    Ready

    5.2

    The Request/Response Model

    F · Foundation

    Ready

    5.3

    Address Maps and Decoding

    F · Foundation

    Ready

    5.4

    Register Semantics

    W · Working

    Ready

    5.5

    Combined and Split Transactions

    W · Working

    Ready

    5.6

    Independent Channels

    W · Working

    Ready

    5.7

    Posted and Non-Posted Writes

    W · Working

    Ready

    5.8

    Bursts

    W · Working

    Ready

    5.9

    Alignment, Strobes and Narrow Transfers

    W · Working

    Ready

    5.10

    Boundary Rules

    S · Senior

    Ready

    5.11

    Width and Endianness Conversion

    S · Senior

    Ready

    5.12

    Transaction Attributes

    S · Senior

    Ready

    5.13

    Atomics

    S · Senior

    Ready

    5.14

    Sideband or In-Band

    W · Working

    Ready

    5.15

    Interrupts and Notification

    W · Working

    Ready

    5.16

    Descriptors, Rings and Doorbells

    S · Senior

    Ready

    5.17

    Bridges and Protocol Conversion

    S · Senior

    Ready

    —

    Protocols compared

    all levels

    Ready

    —

    Drills and checkpoint

    all levels

    Ready

    Every lesson in this part is ready. Work through them in order: each one sets up the problem the next one solves.

    Tip

    DCLink in this part. Step 4: read and write transactions with addresses, incrementing bursts and an error completion (DCLink moves whole flits, so it has no byte enables). DCLink is the small protocol you build across the course; see How to use this course.

    Where other courses go deeper

    This course teaches why protocols are designed the way they are. These lessons show how to build or sign off the same ideas, so this part links to them instead of repeating them.

    • RTL: Arbitration

    Related topics

    • Course hub

    • Previous: Part 4 · Flow Control

    • Next: Part 6 · Concurrency and Performance

    PreviousNext: Reads and Writes Are Not Symmetric

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    Up nextReads and Writes Are Not Symmetric

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    See also

    • How to Use This Course
    • Reading Paths
    • Concept Map