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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding
    • Register Semantics
    • Combined and Split Transactions
    • Independent Channels
    • Posted and Non-Posted Writes
    • Bursts
    • Alignment, Strobes and Narrow Transfers
    • Boundary Rules
    • Width and Endianness Conversion
    • Transaction Attributes
    • Atomics
    • Sideband or In-Band
    • Interrupts and Notification
    • Descriptors, Rings and Doorbells
    • Bridges and Protocol Conversion
    • Protocols Compared: Transactions
    • Drills: Transactions
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 5: Transactions
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 5: Transactions
  4. Atomics

Part 5 · Transactions · Senior (S)

Atomics

Three ways to make a read-modify-write indivisible: lock the path, try an exclusive pair and retry if someone interfered, or send the operation to where the data lives. Cost and scaling of each.

On this page

    Note

    Level: Senior (S) · Answers: What exactly is being asked?

    Before this: Combined and Split Transactions

    Two processors share a counter in memory. Each increments it a million times: read the value, add one, write it back. At the end the counter should read two million. It reads about 1.3 million. Hundreds of thousands of increments vanished, because one processor's read landed between the other's read and write, and one of the two writes overwrote the other.

    How does a protocol make a read-modify-write indivisible when many requesters share the data?

    The obvious answer, and why it breaks

    The obvious fix is to stop everyone else while you do it: lock the bus, read, modify, write, unlock. On a single shared bus with two masters that works. In a modern fabric with many paths, many targets and many requests in flight, "stop everyone" means stalling traffic that has nothing to do with the counter, across the whole fabric, for a full read round trip. It is correct and it does not scale.

    The idea: three ways to be atomic

    Method

    How

    Cost

    Scales?

    Locked transfers

    Hold the path (or the target) from the read until the write; nobody else gets in

    Blocks unrelated traffic for a round trip

    Poorly

    Exclusive pair (load-linked / store-conditional)

    Exclusive read marks the location; exclusive write succeeds only if nobody wrote it in between, and reports success or failure; software retries on failure

    A monitor per target; retries under contention

    Well, while contention is low

    Far atomic

    Send the operation itself (fetch-and-add, swap, compare-and-swap) to the target, which does it in one step and returns the old value

    Atomic logic at the target; a non-posted request

    Very well: one round trip, no retries

    An exclusive write succeeds only if nobody else wrote the location since the exclusive read; a failure leaves memory unchanged and software tries again.

    How an exclusive access knows it failed

    A monitor near the target (or in the interconnect) remembers, per requester, the address of its last exclusive read. Any ordinary write to that address by someone else clears the mark. When the exclusive write arrives, the monitor checks the mark: still set, the write goes ahead and the response says success; cleared, the write is dropped and the response says failure. The response status is the only way the requester learns which, so it must be a distinct status, not just "OK".

    The design space

    Situation

    Choose

    Because

    Single bus, two masters, rare atomics

    Locked transfers are tolerable

    There is little traffic to block

    Processors synchronising through caches or memory

    Exclusive pairs

    Cheap when uncontended; needs only a monitor

    Many requesters hammering one counter or queue index

    Far atomics

    No retries; one round trip each, however many contend

    Devices updating shared counters across a link

    Far atomics

    The device has no cache and no cheap way to retry

    How real protocols chose

    Protocol

    Atomics

    AXI

    Exclusive accesses: an exclusive read and an exclusive write (AxLOCK). Success returns EXOKAY; failure returns OKAY and leaves memory unchanged. AXI4 removed locked transfers.

    PCI Express

    AtomicOps: FetchAdd, Swap and CAS, non-posted; the completion returns the original value. Every switch on the path must support routing them.

    AHB

    Locked transfers (HMASTLOCK): the locked sequence is not interrupted by other masters.

    What breaks

    • The lost increment in the opening: plain read-modify-write on shared data. Any of the three methods fixes it.

    • Livelock with exclusives: two requesters (illustrative) keep clearing each other's marks, so both keep failing. Real systems add back-off, or guarantee forward progress in the monitor.

    • A bridge that drops the exclusive bit (lesson 5.17): the target treats the exclusive write as an ordinary write and answers with plain success. Depending on the protocol, that either reads as "failed" for ever (software loops) or as success without atomicity (silent corruption).

    Why this matters

    Principal lens. Choose the atomic mechanism by contention and distance. Exclusives are cheap and local but degrade under contention; far atomics cost logic at the target but give one round trip per operation however many requesters contend, which is why accelerators and devices use them for shared queues and counters. Whatever you choose, check every bridge and converter on the path preserves it, and verify the failure path, not only the success path.

    Interview

    Asked: "How does an exclusive access know it failed?"

    Weak answer: It reads the value back.

    Strong answer: A monitor near the target remembers each requester's last exclusive-read address, and any write to it by someone else clears that mark. When the exclusive write arrives, the monitor checks the mark: if it's still set the write happens and the response says success; if not, the write is dropped and the response says failure. In AXI, success is EXOKAY and failure is OKAY with memory unchanged, and software retries the whole read-modify-write.

    Follow-ups: (1) Why do locked transfers scale badly? (2) When would you use a far atomic instead?

    Check yourself Why can't an exclusive write report failure with an ordinary OK status alone?

    The requester must distinguish success from failure to know whether to retry; that needs a distinct status (in AXI, EXOKAY for success, OKAY for failure).

    Check yourself Sixty-four accelerator threads increment one counter in memory across a link. Exclusives or far atomics?

    Far atomics: one round trip each with no retries. Exclusives would fail and retry heavily under that contention.

    Key takeaways

    • Atomicity can come from locking the path, from an exclusive pair that detects interference, or from sending the operation to the data.

    • Exclusive accesses need a monitor and a distinct success status; software retries on failure.

    • Far atomics scale best under contention; locked transfers scale worst.

    Keep going

    Next: Lesson 5.14, Sideband or In-Band. A dedicated wire, or a message on the main path? Interrupts, resets and other signals.

    Related topics

    • Part 5 overview: Transactions

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    See also

    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding