Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding
    • Register Semantics
    • Combined and Split Transactions
    • Independent Channels
    • Posted and Non-Posted Writes
    • Bursts
    • Alignment, Strobes and Narrow Transfers
    • Boundary Rules
    • Width and Endianness Conversion
    • Transaction Attributes
    • Atomics
    • Sideband or In-Band
    • Interrupts and Notification
    • Descriptors, Rings and Doorbells
    • Bridges and Protocol Conversion
    • Protocols Compared: Transactions
    • Drills: Transactions
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
Loading lesson

‹Part 5: Transactions
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 5: Transactions
  4. Reads and Writes Are Not Symmetric

Part 5 · Transactions · Foundation (F)

Reads and Writes Are Not Symmetric

A read and a write look like mirror images, but they are not: data flows in opposite directions, "done" means different things, and only one of them can be hidden behind a buffer.

On this page

    Note

    Level: Foundation (F) · Answers: What exactly is being asked?

    Before this: Memory, Message and Stream Semantics

    A processor runs a loop that copies a buffer: read a word, write it somewhere else, repeat. Speeding up the memory's write path makes almost no difference to the loop. Speeding up the read path makes it nearly twice as fast. Reads and writes both move one word across the same bus, so why does one matter so much more?

    Why are reads and writes not symmetric, and what does that mean for protocol design?

    The obvious answer, and why it breaks

    The obvious picture is that a read and a write are the same transaction pointed in opposite directions: an address goes out, a word moves, done. But look at what the requester needs before it can carry on. After a write, it needs nothing back: the data has left, and something downstream can finish the job. After a read, it needs the data itself, and that cannot arrive until the request has reached the target and the answer has come all the way back. A read always costs a full round trip; a write need not cost any.

    The idea: data flows differently, so "done" means different things

    Read

    Write

    Goes out

    Address (and size, ID, attributes)

    Address and data

    Comes back

    The data, plus a status

    Only a status, or nothing at all

    The requester can continue when

    The data has arrived: a full round trip

    The data has been handed off: possibly at once

    Can a buffer hide the latency?

    No: nothing downstream can answer for the target

    Yes: a buffer can accept the write and finish it later

    Typical bottleneck

    Latency (the consumer waits)

    Bandwidth (data must keep moving)

    A read costs a round trip before the requester can use its data; a write can be accepted by the interconnect and completed later.

    Worked numbers

    A copy loop with illustrative numbers: memory 100 ns away, and a write buffer in the interconnect that accepts a write in 2 ns.

    Diagram
    Per word copied:
      read:  request out + data back                    = 100 ns  (the loop must wait for it)
      write: handed to the write buffer                 =   2 ns  (memory finishes it later)
      loop time per word                                = 102 ns
    Make writes twice as fast (1 ns):   101 ns per word  (1% faster)
    Make reads  twice as fast (50 ns):   52 ns per word  (nearly 2x faster)

    The write path matters only for bandwidth: the buffer must drain as fast as writes arrive, or it fills and writes start to wait too. The read path matters for latency, and latency is what the loop sees.

    Consequences for protocol design

    • Separate read and write paths. Reads and writes carry data in opposite directions, so a protocol that gives each its own channels can move read data and write data at the same time (lesson 5.6).

    • Many reads in flight. Since a read's latency cannot be hidden, protocols let a requester issue many reads before the first answer returns (Part 6).

    • Writes may not wait for an answer. A posted write gets no response at all, and its requester never waits (lesson 5.7). The price is knowing less about when, or whether, the write finished.

    • Reads are where ordering bites. A read can be answered from a buffer only if no newer write to the same address is still waiting in another buffer (lesson 7.8).

    How real protocols treat them

    Protocol

    Reads

    Writes

    AXI

    Read address channel out; read data channel back, with a status on every beat

    Write address and write data channels out; one write response per burst

    PCI Express

    Non-posted: every read gets a completion carrying the data

    Memory writes are posted: no completion comes back

    APB

    One transfer at a time; the requester waits for PREADY

    Same: the requester waits for PREADY

    What breaks

    A design team (illustrative) sized a bridge's buffers with equal space for reads and writes, reasoning that traffic was half each. Writes flowed through at full rate because the bridge accepted them at once. Reads queued behind the slow target, each holding a requester idle, and the requesters starved. The writes needed buffer space for bandwidth; the reads needed more outstanding slots to cover their latency, which a symmetric design never gave them.

    Why this matters

    Senior lens. When a design talks about "transactions" as one thing, split them. Ask separately: what limits read latency (round-trip path, target), how many reads can be outstanding, and how fast can writes drain. Most performance problems on a shared bus turn out to be read latency that nobody budgeted, hidden behind a write path that looked fine.

    Interview

    Asked: "Why is a read harder to make fast than a write?"

    Weak answer: Reads are bigger.

    Strong answer: A read can't finish until its data has gone to the target and come back, so the requester always pays a full round trip, and nothing in between can answer for the target. A write carries its data with it, so a buffer can accept it immediately and finish it later; the requester only needs bandwidth, not low latency. That's why protocols post writes and allow many reads in flight.

    Follow-ups: (1) What does a posted write give up? (2) Why do protocols separate read and write channels?

    Check yourself A loop reads a word and writes a word each iteration. Read latency is 80 ns, write hand-off is 4 ns. What dominates the loop time?

    The read: 80 of 84 ns per iteration. Halving the write time saves 2 ns; halving the read time saves 40 ns.

    Check yourself Why can't a write buffer do for reads what it does for writes?

    A read needs data that only the target has; a buffer in between cannot answer for it (unless it holds a copy, which is a cache, with all the coherence questions that brings).

    Key takeaways

    • A read must wait a full round trip for its data; a write carries its data and can be handed off at once.

    • Read latency stalls the requester; write performance is about bandwidth and buffering.

    • Protocols separate read and write paths, allow many reads in flight, and often post writes.

    Keep going

    Next: Lesson 5.2, The Request/Response Model. Every transaction is a request and a response. What each one carries, and why every request must get exactly one answer.

    Related topics

    • Part 5 overview: Transactions

    Previous

    68 / 234

    Next: The Request/Response Model

    Up next

    Up nextThe Request/Response Model

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Address Maps and Decoding
    • Register Semantics
    • Combined and Split Transactions