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Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • How to Read the Diagrams
  • Part 0: What Is a Protocol?10
  • Part 1: Timing and Clocking11
  • Part 2: Encoding and Framing12
  • Part 3: Handshakes13
  • Part 4: Flow Control17
  • Part 5: Transactions19
    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding
    • Register Semantics
    • Combined and Split Transactions
    • Independent Channels
    • Posted and Non-Posted Writes
    • Bursts
    • Alignment, Strobes and Narrow Transfers
    • Boundary Rules
    • Width and Endianness Conversion
    • Transaction Attributes
    • Atomics
    • Sideband or In-Band
    • Interrupts and Notification
    • Descriptors, Rings and Doorbells
    • Bridges and Protocol Conversion
    • Protocols Compared: Transactions
    • Drills: Transactions
  • Part 6: Concurrency and Performance17
  • Part 7: Ordering13
  • Part 8: Sharing and Arbitration12
  • Part 9: Deadlock and Liveness13
  • Part 10: Reliability and Recovery20
  • Part 11: Bring-Up and Link Management10
  • Part 12: Power8
  • Part 13: Shared State and Coherence9
  • Part 14: Security and Isolation7
  • Part 15: Specifying and Verifying11
  • Part 16: Protocols Dissected17
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
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‹Part 5: Transactions
  1. Topics
  2. First Principles of Hardware Protocols
  3. Part 5: Transactions
  4. Bridges and Protocol Conversion

Part 5 · Transactions · Senior (S)

Bridges and Protocol Conversion

A bridge translates transactions from one protocol to another. What maps cleanly, what must be emulated, and what cannot be carried across at all: bursts, concurrency, ordering, errors, atomics and attributes.

On this page

    Note

    Level: Senior (S) · Answers: What exactly is being asked?

    Before this: Width and Endianness Conversion, Atomics

    A processor uses exclusive accesses on a semaphore that lives in a peripheral behind an AXI-to-APB bridge. On the AXI side, the exclusive write must report either success or failure. APB has no notion of exclusive access. The bridge turns the exclusive write into an ordinary APB write and reports... what? Whatever it reports, the processor's lock is now either never acquired, or acquired without being atomic.

    What does a bridge between two protocols translate, and what can it not carry across?

    The obvious answer, and why it breaks

    The obvious bridge maps fields: an address is an address, data is data, a write is a write. For the common case, single writes and reads with no errors, it works. But every protocol has features the other may lack: bursts, many outstanding transactions, out-of-order responses, specific error codes, atomics, attributes, ordering rules. For each one the bridge must emulate it, approximate it, or refuse it, and each choice changes what the requester can rely on.

    The idea: map, emulate, or lose

    Everything the AXI side can express must be mapped, emulated or refused before it reaches a protocol that moves one transfer at a time.

    Feature

    AXI side

    APB side

    What the bridge does

    Bursts

    Up to 256 beats

    None

    Splits each burst into single transfers (emulated: slower)

    Outstanding transactions

    Many, with IDs

    One

    Queues requests and serialises them (emulated: concurrency lost)

    Out-of-order responses

    Allowed between IDs

    Impossible

    Responses come back in order (harmless, but lost)

    Read/write concurrency

    Separate channels

    One transfer at a time

    Arbitrates between reads and writes; their relative order is the bridge's choice

    Errors

    OKAY, SLVERR, DECERR

    PSLVERR

    PSLVERR becomes SLVERR; a burst's response must combine its transfers' errors

    Partial writes

    WSTRB per byte

    PSTRB only from APB4

    Before APB4: refuse, or write whole words (dangerous)

    Exclusive accesses

    Exclusive read and write

    None

    Answer the exclusive write as failed (OKAY), so software's lock is never acquired, or implement a monitor in the bridge

    Attributes

    AxPROT, AxCACHE, AxQOS

    PPROT only from APB4

    Map protection bits; cache and priority attributes stop at the bridge

    Three kinds of outcome appear in the last column. Some features are emulated at a cost (bursts become many transfers). Some are lost harmlessly (out-of-order freedom the requester did not need). Some are lost dangerously (exclusives, partial writes): the requester believes it got a guarantee it did not.

    General rules for any bridge

    • Never fake success. If the far side cannot do something, return an error or a defined failure, never a plain OK.

    • Respect both sides' rules at once: the near side's response rules (one response per burst, ordering per ID) and the far side's limits (burst lengths, boundaries, outstanding count).

    • Decide ordering explicitly. A bridge that reorders reads and writes, or posts writes the near side expects to be non-posted, changes the guarantees software relies on (lesson 7.11).

    • Document what is lost. The bridge's datasheet should say which features it maps, emulates and refuses.

    How real systems chose

    Bridge

    Typical behaviour

    AXI to APB

    Serialises everything into single APB transfers; maps PSLVERR to SLVERR; carries PSTRB and PPROT when the APB side is APB4.

    AXI to PCI Express

    Maps AXI reads to non-posted reads and AXI writes to posted memory writes, then must provide an AXI write response even though no completion comes back from PCIe (an early acknowledgement), and must keep PCIe's and AXI's ordering rules consistent (Part 7).

    What breaks

    The opening semaphore (illustrative): the bridge answered exclusive writes with plain OKAY, which in AXI means "exclusive failed". The processor's lock routine retried for ever. A second version of the bridge "fixed" it by answering EXOKAY, so locks were acquired but not atomic, and two processors occasionally entered the same critical section. The real fix was to move the semaphore into memory that supports exclusive accesses, and to make the bridge return an error for exclusive accesses so the mistake would be caught at once.

    Why this matters

    Principal lens. A bridge is a contract translator, and the dangerous part is what it silently drops. In any review, list every feature of the richer protocol (bursts, IDs, ordering, errors, atomics, partial writes, attributes, posting) and ask, for each one, whether the bridge maps, emulates, refuses or fakes it. Faking is never acceptable. Then check that software and the address map never route an operation through a bridge that cannot honour it.

    Interview

    Asked: "What can go wrong in an AXI-to-APB bridge?"

    Weak answer: It's slower because APB is slower.

    Strong answer: Speed is the small part: bursts get split and outstanding transactions serialised. The real risks are lost guarantees. Exclusive accesses can't be carried, so the bridge must report them as failed or as errors, never fake success. Before APB4 there are no strobes, so partial writes can't be done safely. Cache and QoS attributes stop at the bridge, a burst's single response has to merge the errors of all its transfers, and the bridge decides the order of reads versus writes. Each lost feature has to be refused loudly, not faked.

    Follow-ups: (1) What should a bridge return for an operation it can't perform? (2) How does an AXI-to-PCIe bridge produce a write response?

    Check yourself An AXI INCR8 write goes through an AXI-to-APB bridge. How many APB transfers, and how many AXI write responses?

    Eight APB transfers (one per beat), and one AXI write response, which must report an error if any of the eight failed.

    Check yourself Why is faking EXOKAY worse than returning OKAY for an exclusive write the bridge cannot honour?

    OKAY makes the lock routine retry (a visible hang); EXOKAY makes it believe it has the lock without atomicity, which corrupts data silently.

    Key takeaways

    • A bridge maps what both protocols share, emulates some features at a cost, and must refuse the rest.

    • Bursts and concurrency are usually emulated; exclusives, partial writes and attributes are often lost.

    • Never fake success: refuse what cannot be honoured, and document what is lost.

    Keep going

    Next: Protocols Compared: Transactions. How a dozen protocols describe a transaction, side by side.

    Related topics

    • Part 5 overview: Transactions

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    See also

    • Reads and Writes Are Not Symmetric
    • The Request/Response Model
    • Address Maps and Decoding