Read across for one protocol; read down to see how differently the same questions are answered.
APB | AHB | AXI | PCI Express | DCLink | |
|---|---|---|---|---|---|
Split or combined | Combined, wait states | Combined (original AHB: SPLIT and RETRY) | Split: five channels, IDs | Split: requests and completions, tags | Split: RD/WR and CPL |
Bursts | None | Yes | FIXED, INCR (up to 256 in AXI4), WRAP (2–16) | One packet carries up to its maximum payload | Incrementing, up to 15 flits |
Writes posted? | No | No | No: one response per burst (early acknowledgement possible) | Memory writes yes; configuration and I/O no | No |
Error responses | PSLVERR (APB3) | ERROR response | SLVERR, DECERR | Completion status | CPL status ERR |
Partial writes | PSTRB (APB4) | Size and address | WSTRB per byte lane | Byte enables for first and last data word | Whole flits only |
Atomics | None | Locked transfers | Exclusive accesses (locks removed in AXI4) | AtomicOps: FetchAdd, Swap, CAS | None |
Attributes | PPROT (APB4) | Protection signals | AxCACHE, AxPROT, AxQOS | Traffic class, Relaxed Ordering, No Snoop | None |
Interrupts | Wires | Wires | Wires | MSI / MSI-X messages (posted writes) | None |
Boundary rule | — | 1 KB for bursts | No burst crosses 4 KB | No request crosses 4 KB | No burst past the end of memory |
The simpler the target, the simpler the transaction: APB serves registers one at a time, so it needs no bursts, IDs or posting.
High-performance protocols split transactions and add IDs, so many can be in flight (Part 6).
Posting appears where round trips are long: PCIe posts memory writes; on-chip AXI keeps a response per write but lets the fabric answer early.
Atomics, attributes and strobes are where bridges lose information (lesson 5.17).