A 128-bit processor port must reach a 32-bit peripheral bus. A single 16-beat burst on the wide side becomes 64 beats on the narrow side, and the narrow protocol allows at most 16 per burst. Meanwhile a network packet arrives with its 32-bit length field stored most-significant byte first, while the processor stores numbers least-significant byte first. The bytes are all there. Their arrangement is wrong for the other side.
What does it take to join buses of different widths, or different byte orders, and what cannot be carried across?
The obvious converter rewires: split each wide beat into narrow beats, or glue narrow beats into wide ones. For full, aligned, incrementing transfers that is nearly all it does. But a burst also has a length limit, a type (wrapping, fixed), strobes, a boundary rule, and sometimes atomicity. Each of these has to be rebuilt on the other side, and some cannot be rebuilt exactly.
Converter | Does | Must also handle | Costs |
|---|---|---|---|
Downsizer (wide → narrow) | Splits each beat into width ratio narrow beats, in address order | Longer bursts than the narrow side allows (split them); narrow-beat strobes; skipping beats whose strobes are all 0; wrapping bursts | Bandwidth: the narrow side needs ratio × more beats |
Upsizer (narrow → wide) | Packs consecutive narrow beats into one wide beat | Partial wide beats at the start and end (strobes); bursts that are not incrementing; reads that must return only the requested bytes | Latency (waiting to fill a wide beat) and buffering |
Illustrative numbers: a 16-beat burst of 128-bit beats into a 32-bit protocol whose bursts are at most 16 beats.
Wide side: 16 beats x 16 bytes = 256 bytes
Narrow side: 256 bytes / 4 bytes per beat = 64 beats
Limit 16 beats per burst -> 64 / 16 = 4 narrow bursts
Each wide beat becomes 4 narrow beats; the write response is sent upstream only after all 4 narrow bursts are acknowledged
Bandwidth: if both sides run at the same clock, the narrow side takes 4x as longTwo consequences follow. The downsizer must merge four narrow responses into one wide response, choosing what to report if one fails. And a wrapping burst may not map to a legal wrapping burst on the narrow side: a WRAP4 of 16-byte beats wraps at 64 bytes, which needs a WRAP16 of 4-byte beats; if the narrow protocol allows no 16-beat wrap, the converter must issue incrementing pieces in the same order instead.
A multi-byte number stored in memory occupies several addresses. Little-endian stores the least-significant byte at the lowest address; big-endian stores the most-significant byte there. The value 0x11223344 at address 0x100:
Address | 0x100 | 0x101 | 0x102 | 0x103 |
|---|---|---|---|---|
Little-endian | 44 | 33 | 22 | 11 |
Big-endian | 11 | 22 | 33 | 44 |
A bus moves bytes in lanes, and lane n always carries address n within the word (lesson 5.9). So a bus does not need to know byte order to move data correctly: bytes go to the addresses they came from. Byte order matters only where something interprets several bytes as one number: a processor loading a word, a device register, a header field. Converting byte order is therefore a job for the side that interprets the value (usually software, or a device that knows its field layout), not for the bus. A converter that "swaps bytes" for all traffic corrupts every byte array that passes through it.
Where | Choice |
|---|---|
Arm and RISC-V processors | Little-endian by default. |
Internet protocol headers | Big-endian ("network byte order"); software converts multi-byte fields when it reads or writes them. |
AXI interconnects | Width converters (upsizers and downsizers) are standard interconnect components; they rebuild bursts and strobes and respect the 4 KB rule. |
A bridge (illustrative) between a big-endian legacy device and a little-endian processor swapped the bytes of every 32-bit word in hardware. Register reads worked. Then the device was used for DMA of a byte stream, and every received string came out in groups of four, reversed. Byte order belonged to the register values, which the driver could have converted; the stream needed bytes left alone. The fix was to remove the hardware swap and convert register values in the driver.
Each 8-byte beat becomes four 2-byte beats: 16 narrow beats (32 bytes in all).
In software (or the device) when it reads the field as a number, not on the bus: the bus carries bytes to their addresses unchanged.
Downsizers split beats and rebuild bursts, strobes and responses; upsizers pack beats and must handle partial beats.
Width conversion can split one burst into several, change what wrapping means, and costs bandwidth on the narrow side.
Buses move bytes to addresses; byte order matters only where bytes are read as a number, so convert it there.