Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
A read must wait a full round trip for its data and nothing in between can answer for the target; a write carries its data and can be accepted by a buffer at once.
A default target accepts it and returns a decode error (AXI DECERR), so the requester gets its one response and software gets a precise fault.
Any extra read (a debugger, a retry, a duplicate) destroys events. Prefer W1C status, with set winning over a same-cycle clear.
Each kind of information gets its own valid/ready channel: reads and writes move together, addresses run ahead of data, and each channel can be pipelined alone.
Boundary 16, block 0x30–0x3F: 0x38, 0x3C, 0x30, 0x34.
One beat to word 0x0 with strobes for lanes 5–7 (11100000).
Decoders and address translation look at the start address once; a crossing burst's tail could belong to another target or another page.
A monitor tracks the exclusive read's address per requester; any other write clears it; the exclusive write's response reports success (EXOKAY) or failure (OKAY).
Task. A DMA engine on a 64-bit AXI port copies 1,000 bytes from 0x0FF4 to a peripheral FIFO behind an AXI-to-APB bridge (32-bit APB4). Describe the bursts on the read side, what reaches the FIFO, and what could go wrong.
Read side: the copy runs from 0x0FF4 to 0x13DB and crosses the 4 KB boundary at 0x1000, so it needs two bursts. First, 2 beats covering words 0x0FF0 and 0x0FF8 (the engine ignores bytes 0x0FF0–0x0FF3, which it did not ask for). Second, an INCR burst of 124 beats from 0x1000, within the 256-beat limit, its last beat half used. Write side: the FIFO sits behind one address, so FIXED bursts (or single writes), never INCR, which would walk past the FIFO into other registers. The bridge turns each 64-bit beat into two 32-bit APB4 transfers, uses PSTRB for a partial last word, and returns one AXI response per burst that reports any PSLVERR. Risks: the FIFO address marked bufferable or modifiable (writes merged or delayed), a partial word written without strobes, and an INCR burst aimed at the FIFO.
The request's ID (when several are outstanding) and a status.
A target that answers at several addresses because its decoder ignores some address bits.
Otherwise an event arriving in the clearing cycle is lost.
IDs or tags, buffering in targets and requesters, and ordering and deadlock rules.
A status back to the requester, and knowing when the write landed.
A FIFO or data register behind one address: every beat goes to the same address.
Two beats: word 0x00 lane 7 (10000000), word 0x08 lane 0 (00000001).
Where bytes are interpreted as a number (software or the device), not on the bus.
At ~149 million small packets per second an interrupt per packet is impossible; polling the ring has no per-event cost.
Empty when tail = head; full when tail − head = ring size.