A testbench is a set of concurrent processes that must share data, arbitrate resources and agree when the test is over. SystemVerilog provides three primitives for this, event, semaphore and mailbox, plus the fork family and process handles for thread control.
Primitive | Carries data | Blocking | Typical use |
|---|---|---|---|
event | No | @ and wait block | Done flags, phase sync |
semaphore | No, keys only | get blocks | Resource arbitration |
mailbox | Yes | put and get block | Producer-consumer pipes |
Lesson | What it covers |
|---|---|
Trigger versus wait, triggered, handle passing and wait_order. | |
Keys, bus arbitration, deadlock and backoff fixes. | |
Bounded versus unbounded, typed handles and sizing. | |
Join variants, loop capture, disable fork, wait fork and process. | |
Synchronization Patterns: Handshakes, Phasing and Objections | Completion counters, objections with drain, races and barriers. |
A deterministic bench tying every primitive together. |
Mailbox for the items, semaphore for the bus, and an objection counter or completion counter for end of test. Events only signal moments, so they cannot carry the items or arbitrate the bus.